README on the IOBARRIER for CardEngine IO=========================================Due to an unfortunate oversight when the Card Engines were designed,the signals that control access to some peripherals, most notably theSMC91C9111 ethernet controller, are not properly handled.The symptom is that back to back IO with the peripheral returnsunreliable data.  With the SMC chip, you'll see errors about the bankregister being 'screwed'.The cause is that the AEN signal to the SMC chip does not transitionfor every memory access.  It is driven through the CPLD from the CS7line of the CPU's static memory controller which is optimized toeliminate unnecessary transitions.  Yet, the SMC requires a transitionfor every access.  The Sharp website has more information on theeffect of this power conservation feature on peripheral interfacing.The solution is to follow every access to the SMC chip with an accessto another memory region that will force the CPU to release the chipselect line.  Note that it is important to guarantee that the accesswill force the CPU off-chip.  We map a page of SDRAM as if it were anuncacheable IO device and read from it after every SMC IO operation.  SMC IO  BARRIER IOYou might be tempted to believe that we must access another deviceattached to the static memory controller, but the empirical evidenceindicates that this is not so.  Mapping 0x00000000 (flash) and0xc0000000 (SDRAM) appear to have the same effect.  Using SDRAM seemsto be faster.