-------------------------------------------------------------------------                                                             --------  OpenCores IDE Controller                                   --------  ATA/ATAPI-5 Host controller (OCIDEC-3)                     --------                                                             --------  Author: Richard Herveille                                  --------          richard@asics.ws                                   --------          www.asics.ws                                       --------                                                             -----------------------------------------------------------------------------                                                             -------- Copyright (C) 2001, 2002 Richard Herveille                  --------                          richard@asics.ws                   --------                                                             -------- This source file may be used and distributed without        -------- restriction provided that this copyright statement is not   -------- removed from the file and that any derivative work contains -------- the original copyright notice and the associated disclaimer.--------                                                             --------     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     -------- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   -------- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   -------- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      -------- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         -------- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    -------- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   -------- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        -------- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  -------- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  -------- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  -------- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         -------- POSSIBILITY OF SUCH DAMAGE.                                 --------                                                             --------------------------------------------------------------------------- rev.: 1.0 march 8th, 2001. Initial release----  CVS Log----  $Id: atahost_controller.vhd,v 1.1 2002/02/18 14:32:12 rherveille Exp $----  $Date: 2002/02/18 14:32:12 $--  $Revision: 1.1 $--  $Author: rherveille $--  $Locker:  $--  $State: Exp $---- Change History:--               $Log: atahost_controller.vhd,v $--               Revision 1.1  2002/02/18 14:32:12  rherveille--               renamed all files to 'atahost_***.vhd'--               broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'--               changed resD input to generic RESD in ud_cnt.vhd--               changed ID input to generic ID in ro_cnt.vhd--               changed core to reflect changes in ro_cnt.vhd--               removed references to 'count' library--               changed IO names--               added disclaimer--               added CVS log--               moved registers and wishbone signals into 'atahost_wb_slave.vhd'----library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity atahost_controller is	generic(		TWIDTH : natural := 8;                   -- counter width		-- PIO mode 0 settings (@100MHz clock)		PIO_mode0_T1 : natural := 6;             -- 70ns		PIO_mode0_T2 : natural := 28;            -- 290ns		PIO_mode0_T4 : natural := 2;             -- 30ns		PIO_mode0_Teoc : natural := 23;          -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240		-- Multiword DMA mode 0 settings (@100MHz clock)		DMA_mode0_Tm : natural := 4;             -- 50ns		DMA_mode0_Td : natural := 21;            -- 215ns		DMA_mode0_Teoc : natural := 21           -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215	);	port(		clk : in std_logic;  		                    	  -- master clock in		nReset	: in std_logic := '1';                 -- asynchronous active low reset		rst : in std_logic := '0';                    -- synchronous active high reset				irq : out std_logic;                          -- interrupt request signal		-- control / registers		IDEctrl_IDEen,		IDEctrl_rst,		IDEctrl_ppen,		IDEctrl_FATR0,		IDEctrl_FATR1 : in std_logic;                 -- control register settings		a : in unsigned(3 downto 0);                  -- address input		d : in std_logic_vector(31 downto 0);         -- data input		we : in std_logic;                            -- write enable input '1'=write, '0'=read		-- PIO registers		PIO_cmdport_T1,		PIO_cmdport_T2,		PIO_cmdport_T4,		PIO_cmdport_Teoc : in unsigned(7 downto 0);		PIO_cmdport_IORDYen : in std_logic;           -- PIO compatible timing settings			PIO_dport0_T1,		PIO_dport0_T2,		PIO_dport0_T4,		PIO_dport0_Teoc : in unsigned(7 downto 0);		PIO_dport0_IORDYen : in std_logic;            -- PIO data-port device0 timing settings		PIO_dport1_T1,		PIO_dport1_T2,		PIO_dport1_T4,		PIO_dport1_Teoc : in unsigned(7 downto 0);		PIO_dport1_IORDYen : in std_logic;            -- PIO data-port device1 timing settings		PIOsel : in std_logic;                        -- PIO controller select		PIOack : out std_logic;                       -- PIO controller acknowledge		PIOq : out std_logic_vector(15 downto 0);     -- PIO data out		PIOtip : buffer std_logic;                    -- PIO transfer in progress		PIOpp_full : out std_logic;                   -- PIO Write PingPong full		-- DMA registers		DMA_dev0_Td,		DMA_dev0_Tm,		DMA_dev0_Teoc : in unsigned(7 downto 0);      -- DMA timing settings for device0		DMA_dev1_Td,		DMA_dev1_Tm,		DMA_dev1_Teoc : in unsigned(7 downto 0);      -- DMA timing settings for device1		DMActrl_DMAen,		DMActrl_dir,		DMActrl_BeLeC0,		DMActrl_BeLeC1 : in std_logic;                -- DMA settings		DMAsel : in std_logic;                        -- DMA controller select		DMAack : out std_logic;                       -- DMA controller acknowledge		DMAq : out std_logic_vector(31 downto 0);     -- DMA data out		DMAtip : buffer std_logic;                    -- DMA transfer in progress		DMA_dmarq : out std_logic;                    -- Synchronized ATA DMARQ line		DMATxFull : buffer std_logic;                 -- DMA transmit buffer full		DMARxEmpty : buffer std_logic;                -- DMA receive buffer empty		DMA_req : out std_logic;                      -- DMA request to external DMA engine		DMA_ack : in std_logic;                       -- DMA acknowledge from external DMA engine		-- ATA signals		RESETn	: out std_logic;		DDi	: in std_logic_vector(15 downto 0);		DDo : out std_logic_vector(15 downto 0);		DDoe : out std_logic;		DA	: out unsigned(2 downto 0);		CS0n	: out std_logic;		CS1n	: out std_logic;		DMARQ	: in std_logic;		DMACKn	: out std_logic;		DIORn	: out std_logic;		DIOWn	: out std_logic;		IORDY	: in std_logic;		INTRQ	: in std_logic	);end entity atahost_controller;architecture structural of atahost_controller is	--	-- component declarations	--	component atahost_pio_controller is	generic(		TWIDTH : natural := 8;                   -- counter width		-- PIO mode 0 settings (@100MHz clock)		PIO_mode0_T1 : natural := 6;             -- 70ns		PIO_mode0_T2 : natural := 28;            -- 290ns		PIO_mode0_T4 : natural := 2;             -- 30ns		PIO_mode0_Teoc : natural := 23           -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240	);	port(		clk : in std_logic;  		                    	  -- master clock in		nReset	: in std_logic := '1';                 -- asynchronous active low reset		rst : in std_logic := '0';                    -- synchronous active high reset				-- control / registers		IDEctrl_IDEen,		IDEctrl_ppen,		IDEctrl_FATR0,		IDEctrl_FATR1 : in std_logic;		-- PIO registers		cmdport_T1,		cmdport_T2,		cmdport_T4,		cmdport_Teoc : in unsigned(7 downto 0);		cmdport_IORDYen : in std_logic;            -- PIO command port / non-fast timing		dport0_T1,		dport0_T2,		dport0_T4,		dport0_Teoc : in unsigned(7 downto 0);		dport0_IORDYen : in std_logic;             -- PIO mode data-port / fast timing device 0		dport1_T1,		dport1_T2,		dport1_T4,		dport1_Teoc : in unsigned(7 downto 0);		dport1_IORDYen : in std_logic;             -- PIO mode data-port / fast timing device 1		sel : in std_logic;                           -- PIO controller selected		ack : out std_logic;                          -- PIO controller acknowledge		a : in unsigned(3 downto 0);                  -- lower address bits		we : in std_logic;                            -- write enable input		d : in std_logic_vector(15 downto 0);		q : out std_logic_vector(15 downto 0);		PIOreq : out std_logic;                       -- PIO transfer request		PPFull : out std_logic;                       -- PIO Write PingPong Full		go : in std_logic;                            -- start PIO transfer		done : buffer std_logic;                      -- done with PIO transfer		PIOa : out unsigned(3 downto 0);              -- PIO address, address lines towards ATA devices		PIOd : out std_logic_vector(15 downto 0);     -- PIO data, data towards ATA devices		SelDev : buffer std_logic;                    -- Selected Device, Dev-bit in ATA Device/Head register		DDi	: in std_logic_vector(15 downto 0);		DDoe : buffer std_logic;		DIOR	: buffer std_logic;		DIOW	: buffer std_logic;		IORDY	: in std_logic	);	end component atahost_pio_controller;	component atahost_dma_actrl is	generic(		TWIDTH : natural := 8;                     -- counter width		-- DMA mode 0 settings (@100MHz clock)		DMA_mode0_Tm : natural := 4;               -- 50ns		DMA_mode0_Td : natural := 21;              -- 215ns		DMA_mode0_Teoc : natural := 21             -- 215ns ==> T0 - Td - Tm = 480 - 50 - 215 = 215	);	port(		clk : in std_logic;                           -- master clock		nReset : in std_logic;                        -- asynchronous active low reset		rst : in std_logic;                           -- synchronous active high reset		IDEctrl_rst : in std_logic;                   -- IDE control register bit0, 'rst'		sel : in std_logic;                           -- DMA buffers selected		we : in std_logic;                            -- write enable input		ack : out std_logic;		                        -- acknowledge output		dev0_Tm,		dev0_Td,		dev0_Teoc : in unsigned(7 downto 0);          -- DMA mode timing device 0		dev1_Tm,		dev1_Td,		dev1_Teoc : in unsigned(7 downto 0);          -- DMA mode timing device 1		DMActrl_DMAen,		DMActrl_dir,		DMActrl_BeLeC0,		DMActrl_BeLeC1 : in std_logic;                -- control register settings		TxD : in std_logic_vector(31 downto 0);       -- DMA transmit data		TxFull : buffer std_logic;                    -- DMA transmit buffer full		RxQ : out std_logic_vector(31 downto 0);      -- DMA receive data		RxEmpty : buffer std_logic;                   -- DMA receive buffer empty		RxFull : out std_logic;                       -- DMA receive buffer full		DMA_req : out std_logic;                      -- DMA request to external DMA engine		DMA_ack : in std_logic;                       -- DMA acknowledge from external DMA engine		DMARQ : in std_logic;                         -- ATA devices request DMA transfer		SelDev : in std_logic;                        -- Selected device			Go : in std_logic;                            -- Start transfer sequence		Done : out std_logic;                         -- Transfer sequence done		DDi : in std_logic_vector(15 downto 0);       -- Data from ATA DD bus		DDo : out std_logic_vector(15 downto 0);      -- Data towards ATA DD bus		DIOR,		DIOW : buffer std_logic 	);	end component atahost_dma_actrl;