Revision: 1.0
Date: march 22nd, 2001
Author: Richard Herveille
- initial release
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Revision: 1.0a
Date: april 12th, 2001
Author: Richard Herveille
- removed records.vhd
- removed all references to records.vhd, make core compatible with VHDL to Verilog translation tools
- fixed a minor bug where core didn't respond to IDEen bit.
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Revision: 1.1
Date: june 18th, 2001
Author: Richard Herveille
- Changed wishbone address-input from ADR_I(4 downto 0) to ADR_I(6 downto 2)
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Revision: 1.1a
Date: june 19th, 2001
Author: Richard Herveille
- Simplified DAT_O output multiplexor
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Revision: 1.3
Date: July 11th, 2001
Author: Richard Herveille
- renamed 'ata.vhd' to 'atahost.vhd'
- Changed 'go' & 'igo' generation (pio_tctrl.vhdl).
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Revision: 1.4
Date: Februar 17th, 2002
Author: Richard Herveille
- renamed all files to 'atahost_***.vhd'
- broke-up 'counter.vhd' into 'ud_cnt.vhd' and 'ro_cnt.vhd'
- changed resD input to generic RESD in ud_cnt.vhd
- changed ID input to generic ID in ro_cnt.vhd
- changed core to reflect changes in ro_cnt.vhd
- removed references to 'count' library
- changed IO names
- added disclaimer
- added CVS log
- moved registers and wishbone signals into 'atahost_wb_slave.vhd'
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