?? dsp28_ecan.h
字號:
};
/* Allow access to the bit fields or entire register */
union CANRFP_REG {
Uint32 all;
struct CANRFP_BITS bit;
};
/* eCAN Global Acceptance Mask register (CANGAM) bit definitions */
struct CANGAM_BITS { // bits description
Uint16 GAM150:16; // 15:0
Uint16 GAM2816:13; // 28:16
Uint16 rsvd:2; // 30:29
Uint16 AMI:1; // 31 AMI bit
};
/* Allow access to the bit fields or entire register */
union CANGAM_REG {
Uint32 all;
struct CANGAM_BITS bit;
};
/* eCAN Master Control register (CANMC) bit definitions */
struct CANMC_BITS { // bits description
Uint16 MBNR:5; // 4:0 MBX # for CDR bit
Uint16 SRES:1; // 5 Soft reset
Uint16 STM:1; // 6 Self-test mode
Uint16 ABO:1; // 7 Auto bus-on
Uint16 CDR:1; // 8 Change data request
Uint16 WUBA:1; // 9 Wake-up on bus activity
Uint16 DBO:1; // 10 Data-byte order
Uint16 PDR:1; // 11 Power-down mode request
Uint16 CCR:1; // 12 Change configuration request
Uint16 SCM:1; // 13 SCC compatibility mode
Uint16 LNTM:1; // 14 LNT MSB clear bit
Uint16 LNTC:1; // 15 LNT clear bit thru mailbox 16
Uint16 SUSP:1; // 16 SUSPEND free/soft bit
Uint16 rsvd:15; // 31:17 reserved
};
/* Allow access to the bit fields or entire register */
union CANMC_REG {
Uint32 all;
struct CANMC_BITS bit;
};
/* eCAN Bit -timing configuration register (CANBTC) bit definitions */
struct CANBTC_BITS { // bits description
Uint16 TSEG2:3; // 2:0 TSEG2
Uint16 TSEG1:4; // 6:3 TSEG1
Uint16 SAM:1; // 7 Sample-point setting
Uint16 SJW:2; // 9:8 Synchroniztion Jump Width
Uint16 ERM:1; // 10 Edge resynchroniztion mode
Uint16 rsvd1:5; // 15:11 reserved
Uint16 BRP:8; // 23:16 Time quantum prescaler
Uint16 rsvd2:8; // 31:24 reserved
};
/* Allow access to the bit fields or entire register */
union CANBTC_REG {
Uint32 all;
struct CANBTC_BITS bit;
};
/* eCAN Error & Status register (CANES) bit definitions */
struct CANES_BITS { // bits description
Uint16 TM:1; // 0 TM
Uint16 RM:1; // 1 RM
Uint16 rsvd1:1; // 2 reserved
Uint16 PDA:1; // 3 Power-down acknowledge
Uint16 CCE:1; // 4 Change Configuration Enable
Uint16 SMA:1; // 5 Suspend Mode Acknowledge
Uint16 rsvd2:10; // 15:6 reserved
Uint16 EW:1; // 16 EW
Uint16 EP:1; // 17 EP
Uint16 BO:1; // 18 BO
Uint16 ACKE:1; // 19 ACKE
Uint16 SE:1; // 20 SE
Uint16 CRCE:1; // 21 CRCE
Uint16 SA1:1; // 22 SA1
Uint16 BE:1; // 23 BE
Uint16 FE:1; // 24 FE
Uint16 rsvd3:7; // 31:25 reserved
};
/* Allow access to the bit fields or entire register */
union CANES_REG {
Uint32 all;
struct CANES_BITS bit;
};
/* eCAN Transmit Error Counter register (CANTEC) bit definitions */
struct CANTEC_BITS { // bits description
Uint16 TEC:8; // 7:0 TEC
Uint16 rsvd1:8; // 15:8 reserved
Uint16 rsvd2:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANTEC_REG {
Uint32 all;
struct CANTEC_BITS bit;
};
/* eCAN Receive Error Counter register (CANREC) bit definitions */
struct CANREC_BITS { // bits description
Uint16 REC:8; // 7:0 REC
Uint16 rsvd1:8; // 15:8 reserved
Uint16 rsvd2:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANREC_REG {
Uint32 all;
struct CANREC_BITS bit;
};
/* eCAN Global Interrupt Flag 0 (CANGIF0) bit definitions */
struct CANGIF0_BITS { // bits description
Uint16 MIV0:5; // 4:0 Mailbox Interrupt Vector
Uint16 rsvd1:3; // 7:5 reserved
Uint16 WLIF0:1; // 8 WLIF0
Uint16 EPIF0:1; // 9 EPIF0
Uint16 BOIF0:1; // 10 BOIF0
Uint16 RMLIF0:1; // 11 RMLIF0
Uint16 WUIF0:1; // 12 WUIF0
Uint16 WDIF0:1; // 13 WDIF0
Uint16 AAIF0:1; // 14 AAIF0
Uint16 GMIF0:1; // 15 GMIF0
Uint16 TCOIF0:1; // 16 TCOIF0
Uint16 MAIF0:1; // 17 MAIF0
Uint16 rsvd2:14; // 31:18 reserved
};
/* Allow access to the bit fields or entire register */
union CANGIF0_REG {
Uint32 all;
struct CANGIF0_BITS bit;
};
/* eCAN Global Interrupt Mask register (CANGIM) bit definitions */
struct CANGIM_BITS { // bits description
Uint16 I0EN:1; // 0 Interrupt 0 enable
Uint16 I1EN:1; // 1 Interrupt 1 enable
Uint16 SIL:1; // 2 System Interrupt Level
Uint16 rsvd1:5; // 7:3 reserved
Uint16 WLIM:1; // 8 WLIM
Uint16 EPIM:1; // 9 EPIM
Uint16 BOIM:1; // 10 BOIM
Uint16 RMLIM:1; // 11 RMLIM
Uint16 WUIM:1; // 12 WUIM
Uint16 WDIM:1; // 13 WDIM
Uint16 AAIM:1; // 14 AAIM
Uint16 rsvd2:1; // 15 reserved
Uint16 TCOIM:1; // 16 TCOIM
Uint16 MAIM:1; // 17 MAIM
Uint16 rsvd3:14; // 31:18 reserved
};
/* Allow access to the bit fields or entire register */
union CANGIM_REG {
Uint32 all;
struct CANGIM_BITS bit;
};
/* eCAN Global Interrupt Flag 1 (eCANGIF1) bit definitions */
struct CANGIF1_BITS { // bits description
Uint16 MIV1:5; // 4:0 Mailbox Interrupt Vector
Uint16 rsvd1:3; // 7:5 reserved
Uint16 WLIF1:1; // 8 WLIF1
Uint16 EPIF1:1; // 9 EPIF1
Uint16 BOIF1:1; // 11 BOIF1
Uint16 RMLIF1:1; // 11 RMLIF1
Uint16 WUIF1:1; // 12 WUIF1
Uint16 WDIF1:1; // 13 WDIF1
Uint16 AAIF1:1; // 14 AAIF1
Uint16 GMIF1:1; // 15 GMIF1
Uint16 TCOIF1:1; // 16 TCOIF1
Uint16 MAIF1:1; // 17 MAIF1
Uint16 rsvd2:14; // 31:18 reserved
};
/* Allow access to the bit fields or entire register */
union CANGIF1_REG {
Uint32 all;
struct CANGIF1_BITS bit;
};
/* eCAN Mailbox Interrupt Mask register (CANMIM) bit definitions */
struct CANMIM_BITS { // bit description
Uint16 MIM0:1; // 0 MIM for Mailbox 0
Uint16 MIM1:1; // 1 MIM for Mailbox 1
Uint16 MIM2:1; // 2 MIM for Mailbox 2
Uint16 MIM3:1; // 3 MIM for Mailbox 3
Uint16 MIM4:1; // 4 MIM for Mailbox 4
Uint16 MIM5:1; // 5 MIM for Mailbox 5
Uint16 MIM6:1; // 6 MIM for Mailbox 6
Uint16 MIM7:1; // 7 MIM for Mailbox 7
Uint16 MIM8:1; // 8 MIM for Mailbox 8
Uint16 MIM9:1; // 9 MIM for Mailbox 9
Uint16 MIM10:1; // 10 MIM for Mailbox 10
Uint16 MIM11:1; // 11 MIM for Mailbox 11
Uint16 MIM12:1; // 12 MIM for Mailbox 12
Uint16 MIM13:1; // 13 MIM for Mailbox 13
Uint16 MIM14:1; // 14 MIM for Mailbox 14
Uint16 MIM15:1; // 15 MIM for Mailbox 15
Uint16 MIM16:1; // 16 MIM for Mailbox 16
Uint16 MIM17:1; // 17 MIM for Mailbox 17
Uint16 MIM18:1; // 18 MIM for Mailbox 18
Uint16 MIM19:1; // 19 MIM for Mailbox 19
Uint16 MIM20:1; // 20 MIM for Mailbox 20
Uint16 MIM21:1; // 21 MIM for Mailbox 21
Uint16 MIM22:1; // 22 MIM for Mailbox 22
Uint16 MIM23:1; // 23 MIM for Mailbox 23
Uint16 MIM24:1; // 24 MIM for Mailbox 24
Uint16 MIM25:1; // 25 MIM for Mailbox 25
Uint16 MIM26:1; // 26 MIM for Mailbox 26
Uint16 MIM27:1; // 27 MIM for Mailbox 27
Uint16 MIM28:1; // 28 MIM for Mailbox 28
Uint16 MIM29:1; // 29 MIM for Mailbox 29
Uint16 MIM30:1; // 30 MIM for Mailbox 30
Uint16 MIM31:1; // 31 MIM for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANMIM_REG {
Uint32 all;
struct CANMIM_BITS bit;
};
/* eCAN Mailbox Interrupt Level register (CANMIL) bit definitions */
struct CANMIL_BITS { // bit description
Uint16 MIL0:1; // 0 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL1:1; // 1 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL2:1; // 2 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL3:1; // 3 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL4:1; // 4 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL5:1; // 5 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL6:1; // 6 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL7:1; // 7 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL8:1; // 8 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL9:1; // 9 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL10:1; // 10 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL11:1; // 11 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL12:1; // 12 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL13:1; // 13 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL14:1; // 14 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL15:1; // 15 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL16:1; // 16 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL17:1; // 17 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL18:1; // 18 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL19:1; // 19 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL20:1; // 20 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL21:1; // 21 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL22:1; // 22 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL23:1; // 23 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL24:1; // 24 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL25:1; // 25 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL26:1; // 26 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL27:1; // 27 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL28:1; // 28 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL29:1; // 29 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL30:1; // 30 0 -> Int 9.5 1 -> Int 9.6
Uint16 MIL31:1; // 31 0 -> Int 9.5 1 -> Int 9.6
};
/* Allow access to the bit fields or entire register */
union CANMIL_REG {
Uint32 all;
struct CANMIL_BITS bit;
};
/* eCAN Overwrite Protection Control register (CANOPC) bit definitions */
struct CANOPC_BITS { // bit description
Uint16 OPC0:1; // 0 OPC for Mailbox 0
Uint16 OPC1:1; // 1 OPC for Mailbox 1
Uint16 OPC2:1; // 2 OPC for Mailbox 2
Uint16 OPC3:1; // 3 OPC for Mailbox 3
Uint16 OPC4:1; // 4 OPC for Mailbox 4
Uint16 OPC5:1; // 5 OPC for Mailbox 5
Uint16 OPC6:1; // 6 OPC for Mailbox 6
Uint16 OPC7:1; // 7 OPC for Mailbox 7
Uint16 OPC8:1; // 8 OPC for Mailbox 8
Uint16 OPC9:1; // 9 OPC for Mailbox 9
Uint16 OPC10:1; // 10 OPC for Mailbox 10
Uint16 OPC11:1; // 11 OPC for Mailbox 11
Uint16 OPC12:1; // 12 OPC for Mailbox 12
Uint16 OPC13:1; // 13 OPC for Mailbox 13
Uint16 OPC14:1; // 14 OPC for Mailbox 14
Uint16 OPC15:1; // 15 OPC for Mailbox 15
Uint16 OPC16:1; // 16 OPC for Mailbox 16
Uint16 OPC17:1; // 17 OPC for Mailbox 17
Uint16 OPC18:1; // 18 OPC for Mailbox 18
Uint16 OPC19:1; // 19 OPC for Mailbox 19
Uint16 OPC20:1; // 20 OPC for Mailbox 20
Uint16 OPC21:1; // 21 OPC for Mailbox 21
Uint16 OPC22:1; // 22 OPC for Mailbox 22
Uint16 OPC23:1; // 23 OPC for Mailbox 23
Uint16 OPC24:1; // 24 OPC for Mailbox 24
Uint16 OPC25:1; // 25 OPC for Mailbox 25
Uint16 OPC26:1; // 26 OPC for Mailbox 26
Uint16 OPC27:1; // 27 OPC for Mailbox 27
Uint16 OPC28:1; // 28 OPC for Mailbox 28
Uint16 OPC29:1; // 29 OPC for Mailbox 29
Uint16 OPC30:1; // 30 OPC for Mailbox 30
Uint16 OPC31:1; // 31 OPC for Mailbox 31
};
/* Allow access to the bit fields or entire register */
union CANOPC_REG {
Uint32 all;
struct CANOPC_BITS bit;
};
/* eCAN TX I/O Control Register (CANTIOC) bit definitions */
struct CANTIOC_BITS { // bits description
Uint16 TXIN:1; // 0 TXIN
Uint16 TXOUT:1; // 1 TXOUT
Uint16 TXDIR:1; // 2 TXDIR
Uint16 TXFUNC:1; // 3 TXFUNC
Uint16 rsvd1:12; // 15:4 reserved
Uint16 rsvd2:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANTIOC_REG {
Uint32 all;
struct CANTIOC_BITS bit;
};
/* eCAN RX I/O Control Register (CANRIOC) bit definitions */
struct CANRIOC_BITS { // bits description
Uint16 RXIN:1; // 0 RXIN
Uint16 RXOUT:1; // 1 RXOUT
Uint16 RXDIR:1; // 2 RXDIR
Uint16 RXFUNC:1; // 3 RXFUNC
Uint16 rsvd1:12; // 15:4 reserved
Uint16 rsvd2:16; // 31:16 reserved
};
/* Allow access to the bit fields or entire register */
union CANRIOC_REG {
Uint32 all;
struct CANRIOC_BITS bit;
};
/* eCAN Local Network Timer register (CANLNT) bit definitions */
struct CANLNT_BITS { // bit description
Uint16 LNT0:1; // 0 LNT for Mailbox 0
Uint16 LNT1:1; // 1 LNT for Mailbox 1
Uint16 LNT2:1; // 2 LNT for Mailbox 2
Uint16 LNT3:1; // 3 LNT for Mailbox 3
Uint16 LNT4:1; // 4 LNT for Mailbox 4
Uint16 LNT5:1; // 5 LNT for Mailbox 5
Uint16 LNT6:1; // 6 LNT for Mailbox 6
Uint16 LNT7:1; // 7 LNT for Mailbox 7
Uint16 LNT8:1; // 8 LNT for Mailbox 8
Uint16 LNT9:1; // 9 LNT for Mailbox 9
Uint16 LNT10:1; // 10 LNT for Mailbox 10
Uint16 LNT11:1; // 11 LNT for Mailbox 11
Uint16 LNT12:1; // 12 LNT for Mailbox 12
Uint16 LNT13:1; // 13 LNT for Mailbox 13
Uint16 LNT14:1; // 14 LNT for Mailbox 14
Uint16 LNT15:1; // 15 LNT for Mailbox 15
Uint16 LNT16:1; // 16 LNT for Mailbox 16
Uint16 LNT17:1; // 17 LNT for Mailbox 17
Uint16 LNT18:1; // 18 LNT for Mailbox 18
Uint16 LNT19:1; // 19 LNT for Mailbox 19
Uint16 LNT20:1; // 20 LNT for Mailbox 20
Uint16 LNT21:1; // 21 LNT for Mailbox 21
Uint16 LNT22:1; // 22 LNT for Mailbox 22
Uint16 LNT23:1; // 23 LNT for Mailbox 23
Uint16 LNT24:1; // 24 LNT for Mailbox 24
Uint16 LNT25:1; // 25 LNT for Mailbox 25
Uint16 LNT26:1; // 26 LNT for Mailbox 26
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