//====================================================================
//
//====================================================================

#ifndef __OPTION_H__
#define __OPTION_H__

#define FIN         12000000

#define FCLK_400MHZ
//#define FCLK_532MHZ

//#define HDIVN       3       // 1:3:6
#define HDIVN       2       // 1:4:8
#define PDIVN       1

#define VIDEO_DATA_FORMAT_16BPP
//#define VIDEO_DATA_FORMAT_32BPP
//#define VIDEO_DATA_FORMAT_16BPP_2440

#if defined(FCLK_400MHZ)

#define FCLK        (400000000)
#if HDIVN==2
#define HCLK        (FCLK/4)    // 1:4:8
#elif HDIVN==3
#define HCLK        (FCLK/3)    // 1:3:6
#endif
#define PCLK        (HCLK/2)
#define UCLK        (PCLK)

#define M_MDIV		(92)	//Fin=12.0MHz Fout=400.0MHz
#define M_PDIV		(1)
#define M_SDIV	    (1)

#elif defined(FCLK_532MHZ)

#define FCLK        (532000000)
#if HDIVN==2
#define HCLK        (FCLK/4)    // 1:4:8
#elif HDIVN==3
#define HCLK        (FCLK/3)    // 1:3:6
#endif
#define PCLK        (HCLK/2)
#define UCLK        (PCLK)

#define M_MDIV		(125)	//Fin=12.0MHz Fout=532.0MHz
#define M_PDIV		(1)
#define M_SDIV	    (1)

#define HDIVN       2       //1:4:8
#define PDIVN       1

#endif



#define 	_SDRAM_STARTADDRESS     (0x30000000)
#define 	_MMUTT_STARTADDRESS     (0x33ff0000)
#define 	_INT_VIC_STARTADDRESS	(0x33fff000)
#define 	_LCD_FBADDRESS	        (0x31000000)

#define 	_STACK_BASEADDRESS      (0x33f00000)
#define     _NOR_FLASH_BASE         (0x44000000)

#define     _SYS_ADDR_BASE          (0x33f00000)
#define     _SYS_STROE_BASE         (0x44010000)
#define     _SYS_CHS_BASE           (0x44080000)

//If you use ADS1.x, please define ADS10
#define ADS10 1

#endif    //__OPTION_H__