/* ************************************************************************* * Ralink Tech Inc. * 5F., No.36, Taiyuan St., Jhubei City, * Hsinchu County 302, * Taiwan, R.O.C. * * (c) Copyright 2002-2007, Ralink Technology, Inc. * * This program is free software; you can redistribute it and/or modify  *  * it under the terms of the GNU General Public License as published by  *  * the Free Software Foundation; either version 2 of the License, or     *  * (at your option) any later version.                                   *  *                                                                       *  * This program is distributed in the hope that it will be useful,       *  * but WITHOUT ANY WARRANTY; without even the implied warranty of        *  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *  * GNU General Public License for more details.                          *  *                                                                       *  * You should have received a copy of the GNU General Public License     *  * along with this program; if not, write to the                         *  * Free Software Foundation, Inc.,                                       *  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *  *                                                                       *  *************************************************************************	Module Name:	rtmp_mac.h	Abstract:	Ralink Wireless Chip MAC related definition & structures	Revision History:	Who			When		  What	--------	----------	  ----------------------------------------------*/#ifndef __RTMP_MAC_H__#define __RTMP_MAC_H__// =================================================================================// TX / RX ring descriptor format// =================================================================================// the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO.// MAC block use this TXINFO to control the transmission behavior of this frame.#define FIFO_MGMT                 0#define FIFO_HCCA                 1#define FIFO_EDCA                 2//// TXD Wireless Information format for Tx ring and Mgmt Ring////txop : for txop mode// 0:txop for the MPDU frame will be handles by ASIC by register// 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS#ifdef RT_BIG_ENDIANtypedef	struct	PACKED _TXWI_STRUC {	// Word 0	UINT32		PHYMODE:2;	UINT32		TxBF:1;	// 3*3	UINT32		rsv2:1;//	UINT32		rsv2:2;	UINT32		Ifs:1;	// 	UINT32		STBC:2;	//channel bandwidth 20MHz or 40 MHz	UINT32		ShortGI:1;	UINT32		BW:1;	//channel bandwidth 20MHz or 40 MHz	UINT32		MCS:7;		UINT32		rsv:6;	UINT32		txop:2;	//tx back off mode 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.	UINT32		MpduDensity:3;	UINT32		AMPDU:1;		UINT32		TS:1;	UINT32		CFACK:1;	UINT32		MIMOps:1;	// the remote peer is in dynamic MIMO-PS mode	UINT32		FRAG:1;		// 1 to inform TKIP engine this is a fragment.	// Word 1	UINT32		PacketId:4;	UINT32		MPDUtotalByteCount:12;	UINT32		WirelessCliID:8;	UINT32		BAWinSize:6;	UINT32		NSEQ:1;	UINT32		ACK:1;	// Word 2	UINT32		IV;	// Word 3	UINT32		EIV;}	TXWI_STRUC, *PTXWI_STRUC;#elsetypedef	struct	PACKED _TXWI_STRUC {	// Word	0	// ex: 00 03 00 40 means txop = 3, PHYMODE = 1	UINT32		FRAG:1;		// 1 to inform TKIP engine this is a fragment.	UINT32		MIMOps:1;	// the remote peer is in dynamic MIMO-PS mode	UINT32		CFACK:1;	UINT32		TS:1;			UINT32		AMPDU:1;	UINT32		MpduDensity:3;	UINT32		txop:2;	//FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful.	UINT32		rsv:6;		UINT32		MCS:7;	UINT32		BW:1;	//channel bandwidth 20MHz or 40 MHz	UINT32		ShortGI:1;	UINT32		STBC:2;	// 1: STBC support MCS =0-7,   2,3 : RESERVE	UINT32		Ifs:1;	// //	UINT32		rsv2:2;	//channel bandwidth 20MHz or 40 MHz	UINT32		rsv2:1;	UINT32		TxBF:1;	// 3*3	UINT32		PHYMODE:2;  	// Word1	// ex:  1c ff 38 00 means ACK=0, BAWinSize=7, MPDUtotalByteCount = 0x38	UINT32		ACK:1;	UINT32		NSEQ:1;	UINT32		BAWinSize:6;	UINT32		WirelessCliID:8;	UINT32		MPDUtotalByteCount:12;	UINT32		PacketId:4;	//Word2	UINT32		IV;	//Word3	UINT32		EIV;}	TXWI_STRUC, *PTXWI_STRUC;#endif//// RXWI wireless information format, in PBF. invisible in driver. //#ifdef RT_BIG_ENDIANtypedef	struct	PACKED _RXWI_STRUC {	// Word 0	UINT32		TID:4;	UINT32		MPDUtotalByteCount:12;	UINT32		UDF:3;	UINT32		BSSID:3;	UINT32		KeyIndex:2;	UINT32		WirelessCliID:8;	// Word 1	UINT32		PHYMODE:2;              // 1: this RX frame is unicast to me	UINT32		rsv:3;	UINT32		STBC:2;	UINT32		ShortGI:1;	UINT32		BW:1;	UINT32		MCS:7;	UINT32		SEQUENCE:12;	UINT32		FRAG:4;	// Word 2	UINT32		rsv1:8;	UINT32		RSSI2:8;	UINT32		RSSI1:8;	UINT32		RSSI0:8;	// Word 3	/*UINT32		rsv2:16;*/	UINT32		rsv2:8;		UINT32		FOFFSET:8;	// RT35xx		UINT32		SNR1:8;	UINT32		SNR0:8;}	RXWI_STRUC, *PRXWI_STRUC;#elsetypedef	struct	PACKED _RXWI_STRUC {	// Word	0	UINT32		WirelessCliID:8;	UINT32		KeyIndex:2;	UINT32		BSSID:3;	UINT32		UDF:3;	UINT32		MPDUtotalByteCount:12;	UINT32		TID:4;	// Word	1	UINT32		FRAG:4;	UINT32		SEQUENCE:12;	UINT32		MCS:7;	UINT32		BW:1;	UINT32		ShortGI:1;	UINT32		STBC:2;	UINT32		rsv:3;	UINT32		PHYMODE:2;              // 1: this RX frame is unicast to me	//Word2	UINT32		RSSI0:8;	UINT32		RSSI1:8;	UINT32		RSSI2:8;	UINT32		rsv1:8;	//Word3	UINT32		SNR0:8;	UINT32		SNR1:8;	UINT32		FOFFSET:8;	// RT35xx		UINT32		rsv2:8;	/*UINT32		rsv2:16;*/}	RXWI_STRUC, *PRXWI_STRUC;#endif// =================================================================================// Register format// =================================================================================//// SCH/DMA registers - base address 0x0200//// INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit//#define DMA_CSR0		0x200#define INT_SOURCE_CSR		0x200#ifdef RT_BIG_ENDIANtypedef	union	_INT_SOURCE_CSR_STRUC	{	struct	{		UINT32       	:14;		UINT32       	TxCoherent:1;		UINT32       	RxCoherent:1;		UINT32       	GPTimer:1;		UINT32       	AutoWakeup:1;//bit14		UINT32       	TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c		UINT32       	PreTBTT:1;		UINT32       	TBTTInt:1;		UINT32       	RxTxCoherent:1;		UINT32       	MCUCommandINT:1;		UINT32       	MgmtDmaDone:1;		UINT32       	HccaDmaDone:1;		UINT32       	Ac3DmaDone:1;		UINT32       	Ac2DmaDone:1;		UINT32       	Ac1DmaDone:1;		UINT32		Ac0DmaDone:1;		UINT32		RxDone:1;		UINT32		TxDelayINT:1;	//delayed interrupt, not interrupt until several int or time limit hit		UINT32		RxDelayINT:1; //dealyed interrupt	}	field;	UINT32			word;}	INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;#elsetypedef	union	_INT_SOURCE_CSR_STRUC	{	struct	{		UINT32		RxDelayINT:1;		UINT32		TxDelayINT:1;		UINT32		RxDone:1;		UINT32		Ac0DmaDone:1;//4      		UINT32       	Ac1DmaDone:1;		UINT32       	Ac2DmaDone:1;		UINT32       	Ac3DmaDone:1;		UINT32       	HccaDmaDone:1; // bit7		UINT32       	MgmtDmaDone:1;		UINT32       	MCUCommandINT:1;//bit 9		UINT32       	RxTxCoherent:1;		UINT32       	TBTTInt:1;		UINT32       	PreTBTT:1;		UINT32       	TXFifoStatusInt:1;//FIFO Statistics is full, sw should read 0x171c		UINT32       	AutoWakeup:1;//bit14		UINT32       	GPTimer:1;		UINT32       	RxCoherent:1;//bit16		UINT32       	TxCoherent:1;		UINT32       	:14;	}	field;	UINT32			word;} INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;#endif//// INT_MASK_CSR:   Interrupt MASK register.   1: the interrupt is mask OFF//#define INT_MASK_CSR        0x204#ifdef RT_BIG_ENDIANtypedef	union	_INT_MASK_CSR_STRUC	{	struct	{		UINT32       	TxCoherent:1;		UINT32       	RxCoherent:1;		UINT32       	:20;		UINT32       	MCUCommandINT:1;		UINT32       	MgmtDmaDone:1;		UINT32       	HccaDmaDone:1;		UINT32       	Ac3DmaDone:1;		UINT32       	Ac2DmaDone:1;		UINT32       	Ac1DmaDone:1;		UINT32		Ac0DmaDone:1;		UINT32		RxDone:1;		UINT32		TxDelay:1;		UINT32		RXDelay_INT_MSK:1;	}	field;	UINT32			word;}INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;#elsetypedef	union	_INT_MASK_CSR_STRUC	{	struct	{		UINT32		RXDelay_INT_MSK:1;		UINT32		TxDelay:1;		UINT32		RxDone:1;		UINT32		Ac0DmaDone:1;		UINT32       	Ac1DmaDone:1;		UINT32       	Ac2DmaDone:1;		UINT32       	Ac3DmaDone:1;		UINT32       	HccaDmaDone:1;		UINT32       	MgmtDmaDone:1;		UINT32       	MCUCommandINT:1;		UINT32       	:20;		UINT32       	RxCoherent:1;		UINT32       	TxCoherent:1;	}	field;	UINT32			word;} INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;#endif#define WPDMA_GLO_CFG 	0x208#ifdef RT_BIG_ENDIANtypedef	union	_WPDMA_GLO_CFG_STRUC	{	struct	{		UINT32       	HDR_SEG_LEN:16;		UINT32       	RXHdrScater:8;		UINT32       	BigEndian:1;		UINT32       	EnTXWriteBackDDONE:1;		UINT32       	WPDMABurstSIZE:2;		UINT32		RxDMABusy:1;		UINT32		EnableRxDMA:1;		UINT32		TxDMABusy:1;		UINT32		EnableTxDMA:1;	}	field;	UINT32			word;}WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;#elsetypedef	union	_WPDMA_GLO_CFG_STRUC	{	struct	{		UINT32		EnableTxDMA:1;		UINT32		TxDMABusy:1;		UINT32		EnableRxDMA:1;		UINT32		RxDMABusy:1;		UINT32       	WPDMABurstSIZE:2;		UINT32       	EnTXWriteBackDDONE:1;		UINT32       	BigEndian:1;		UINT32       	RXHdrScater:8;		UINT32       	HDR_SEG_LEN:16;	}	field;	UINT32			word;} WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;#endif#define WPDMA_RST_IDX 	0x20c#ifdef RT_BIG_ENDIANtypedef	union	_WPDMA_RST_IDX_STRUC	{	struct	{		UINT32       	:15;		UINT32       	RST_DRX_IDX0:1;		UINT32       	rsv:10;		UINT32       	RST_DTX_IDX5:1;		UINT32       	RST_DTX_IDX4:1;		UINT32		RST_DTX_IDX3:1;		UINT32		RST_DTX_IDX2:1;		UINT32		RST_DTX_IDX1:1;		UINT32		RST_DTX_IDX0:1;	}	field;	UINT32			word;}WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;#elsetypedef	union	_WPDMA_RST_IDX_STRUC	{	struct	{		UINT32		RST_DTX_IDX0:1;		UINT32		RST_DTX_IDX1:1;		UINT32		RST_DTX_IDX2:1;		UINT32		RST_DTX_IDX3:1;		UINT32       	RST_DTX_IDX4:1;		UINT32       	RST_DTX_IDX5:1;		UINT32       	rsv:10;		UINT32       	RST_DRX_IDX0:1;		UINT32       	:15;	}	field;	UINT32			word;} WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;#endif#define DELAY_INT_CFG  0x0210#ifdef RT_BIG_ENDIANtypedef	union	_DELAY_INT_CFG_STRUC	{	struct	{		UINT32       	TXDLY_INT_EN:1;		UINT32       	TXMAX_PINT:7;		UINT32       	TXMAX_PTIME:8;		UINT32       	RXDLY_INT_EN:1;		UINT32       	RXMAX_PINT:7;		UINT32		RXMAX_PTIME:8;	}	field;	UINT32			word;}DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;#elsetypedef	union	_DELAY_INT_CFG_STRUC	{	struct	{		UINT32		RXMAX_PTIME:8;		UINT32       	RXMAX_PINT:7;		UINT32       	RXDLY_INT_EN:1;		UINT32       	TXMAX_PTIME:8;		UINT32       	TXMAX_PINT:7;		UINT32       	TXDLY_INT_EN:1;	}	field;	UINT32			word;} DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;#endif#define WMM_AIFSN_CFG   0x0214#ifdef RT_BIG_ENDIANtypedef	union	_AIFSN_CSR_STRUC	{	struct	{	    UINT32   Rsv:16;	    UINT32   Aifsn3:4;       // for AC_VO	    UINT32   Aifsn2:4;       // for AC_VI	    UINT32   Aifsn1:4;       // for AC_BK	    UINT32   Aifsn0:4;       // for AC_BE	}	field;	UINT32			word;}	AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;#elsetypedef	union	_AIFSN_CSR_STRUC	{	struct	{	    UINT32   Aifsn0:4;       // for AC_BE	    UINT32   Aifsn1:4;       // for AC_BK	    UINT32   Aifsn2:4;       // for AC_VI	    UINT32   Aifsn3:4;       // for AC_VO	    UINT32   Rsv:16;	}	field;	UINT32			word;}	AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;#endif//// CWMIN_CSR: CWmin for each EDCA AC//#define WMM_CWMIN_CFG   0x0218#ifdef RT_BIG_ENDIANtypedef	union	_CWMIN_CSR_STRUC	{	struct	{	    UINT32   Rsv:16;	    UINT32   Cwmin3:4;       // for AC_VO	    UINT32   Cwmin2:4;       // for AC_VI	    UINT32   Cwmin1:4;       // for AC_BK	    UINT32   Cwmin0:4;       // for AC_BE	}	field;	UINT32			word;}	CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;#else