?? can_rx.lst
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ARM COMPILER V2.00f, CAN_RX 20/02/05 14:21:05 PAGE 1
ARM COMPILER V2.00f, COMPILATION OF MODULE CAN_RX
OBJECT MODULE PLACED IN CAN_RX.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe CAN_RX.c THUMB OPTIMIZE(7,SPEED) BROWSE DEBUG TABS(4)
stmt level source
1 /************************************************************/
2 /* PROJECT NAME: CANRX */
3 /* Project: LPC2100 Training course */
4 /* Engineer: T Martin tmartin@hitex.co.uk */
5 /* Filename: main.c */
6 /* Language: C */
7 /* Compiler: Keil ARM V1.3 */
8 /* Assembler: */
9 /* */
10 /************************************************************/
11 /* COPYRIGHT: Hitex UK Ltd 2004 */
12 /* LICENSE: THIS VERSION CREATED FOR FREE DISTRIBUTION */
13 /************************************************************/
14 /* Function: CAN receive example */
15 /* */
16 /* Example */
17 /* */
18 /* Demonstrates the use of the Standard message acceptance */
19 /* and receiving a CAN packet */
20 /* */
21 /* Oscillator frequency 12.000 Mhz */
22 /* Target board Keil MCB21000 */
23 /************************************************************/
24
25
26 #include <LPC21xx.H>
27
28 void CAN1IRQ (void)__irq; //Declare the RX IRQ
29 void InitCAN1(void);
30
31 unsigned int StandardFilter[2] _at_ 0xE0038000; //Declare the standard acceptance filter table
32 unsigned int GroupStdFilter[2] _at_ 0xE0038008;
33 unsigned int IndividualExtFilter[2] _at_ 0xE0038010;
34 unsigned int GroupExtFilter[2] _at_ 0xE0038018;
35
36
37 void InitCAN1(void)
38 {
39 1 IODIR1 = 0x00FF0000; // set all ports to output
40 1 PINSEL1 |= 0x00040000; //Enable Pin 0.25 as CAN1 RX
41 1 C1MOD = 0x00000001; //Set CAN controller into reset
42 1 C1BTR = 0x001C001D; //Set bit timing to 125k
43 1 C1IER = 0x00000001; //Enable the Receive interrupt
44 1 VICVectCntl0 = 0x0000003A; //select a priority slot for a given interrupt
45 1 VICVectAddr0 = (unsigned)CAN1IRQ; //pass the address of the IRQ into the VIC slot
46 1 VICIntEnable = 0x04000000; //enable interrupt
47 1 AFMR = 0x00000001; //Disable the Acceptance filters to allow setup of the table
48 1 StandardFilter[0] = 0x20012002;
49 1 StandardFilter[1] = 0x20032004;
50 1 SFF_sa = 0x00000000; //Set start address of Standard table
51 1 SFF_GRP_sa = 0x00000008; //Set start address of Standard group table
52 1 EFF_sa = 0x00000008; //Set start address of Extended table
53 1 EFF_GRP_sa = 0x00000008; //Set start address of Extended group table
54 1 ENDofTable = 0x00000008; //Set end of table address
55 1 AFMR = 0x00000000; //Enable Acceptance filters
56 1
57 1 C1MOD = 0x00000000; //Release CAN controller
58 1 }
59
ARM COMPILER V2.00f, CAN_RX 20/02/05 14:21:05 PAGE 2
60
61 void CAN1IRQ (void) __irq
62 {
63 1
64 1 IOCLR1 = ~C1RDA<<8; //clear output pins
65 1 IOSET1 = C1RDA<<8; //set output pins
66 1 C1CMR = 0x00000004; //release the recieve buffer
67 1 VICVectAddr = 0x00000000; //Signal the end of interrupt
68 1 }
69
ARM COMPILER V2.00f, CAN_RX 20/02/05 14:21:05 PAGE 3
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** PUBLICS:
PUBLIC CAN1IRQ?A
PUBLIC InitCAN1?T
PUBLIC StandardFilter
PUBLIC GroupStdFilter
PUBLIC IndividualExtFilter
PUBLIC GroupExtFilter
*** DATA SEGMENT '?DT0?AT_E0038000_?1?CAN_RX':
E0038000 StandardFilter:
E0038000 DS 8
*** DATA SEGMENT '?DT0?AT_E0038008_?2?CAN_RX':
E0038008 GroupStdFilter:
E0038008 DS 8
*** DATA SEGMENT '?DT0?AT_E0038010_?3?CAN_RX':
E0038010 IndividualExtFilter:
E0038010 DS 8
*** DATA SEGMENT '?DT0?AT_E0038018_?4?CAN_RX':
E0038018 GroupExtFilter:
E0038018 DS 8
*** CODE SEGMENT '?PR?InitCAN1?T?CAN_RX':
39: IODIR1 = 0x00FF0000; // set all ports to output
00000000 4800 LDR R1,=0xFF0000
00000002 4800 LDR R0,=0xE0028018
00000004 6001 STR R1,[R0,#0x0]
40: PINSEL1 |= 0x00040000; //Enable Pin 0.25 as CAN1 RX
00000006 4800 LDR R2,=0x40000
00000008 4800 LDR R0,=0xE002C004
0000000A 6801 LDR R1,[R0,#0x0]
0000000C 4311 ORR R1,R2
0000000E 6001 STR R1,[R0,#0x0]
41: C1MOD = 0x00000001; //Set CAN controller into reset
00000010 2101 MOV R1,#0x1
00000012 4800 LDR R0,=0xE0044000
00000014 6001 STR R1,[R0,#0x0]
42: C1BTR = 0x001C001D; //Set bit timing to 125k
00000016 4800 LDR R1,=0x1C001D
00000018 4800 LDR R0,=0xE0044014
0000001A 6001 STR R1,[R0,#0x0]
43: C1IER = 0x00000001; //Enable the Receive interrupt
0000001C 2101 MOV R1,#0x1
0000001E 4800 LDR R0,=0xE0044010
00000020 6001 STR R1,[R0,#0x0]
44: VICVectCntl0 = 0x0000003A; //select a priority slot for a given interrupt
00000022 213A MOV R1,#0x3A
00000024 4800 LDR R0,=0xFFFFF200
00000026 6001 STR R1,[R0,#0x0]
45: VICVectAddr0 = (unsigned)CAN1IRQ; //pass the address of the IRQ into the VIC slot
00000028 4900 LDR R1,=CAN1IRQ?A ; CAN1IRQ?A
0000002A 4800 LDR R0,=0xFFFFF100
0000002C 6001 STR R1,[R0,#0x0]
46: VICIntEnable = 0x04000000; //enable interrupt
0000002E 4800 LDR R1,=0x4000000
00000030 4800 LDR R0,=0xFFFFF010
00000032 6001 STR R1,[R0,#0x0]
47: AFMR = 0x00000001; //Disable the Acceptance filters to allow setup of the table
00000034 2101 MOV R1,#0x1
00000036 4800 LDR R0,=0xE003C000
00000038 6001 STR R1,[R0,#0x0]
48: StandardFilter[0] = 0x20012002;
0000003A 4800 LDR R1,=0x20012002
0000003C 4800 LDR R0,=StandardFilter ; StandardFilter
ARM COMPILER V2.00f, CAN_RX 20/02/05 14:21:05 PAGE 4
0000003E 6001 STR R1,[R0,#0x0] ; StandardFilter
49: StandardFilter[1] = 0x20032004;
00000040 4800 LDR R1,=0x20032004
00000042 4800 LDR R0,=StandardFilter + 0x4 ; StandardFilter+4
00000044 6001 STR R1,[R0,#0x0] ; StandardFilter+4
50: SFF_sa = 0x00000000; //Set start address of Standard table
00000046 2100 MOV R1,#0x0
00000048 4800 LDR R0,=0xE003C004
0000004A 6001 STR R1,[R0,#0x0]
51: SFF_GRP_sa = 0x00000008; //Set start address of Standard group table
0000004C 2108 MOV R1,#0x8
0000004E 4800 LDR R0,=0xE003C008
00000050 6001 STR R1,[R0,#0x0]
52: EFF_sa = 0x00000008; //Set start address of Extended table
00000052 2108 MOV R1,#0x8
00000054 4800 LDR R0,=0xE003C00C
00000056 6001 STR R1,[R0,#0x0]
53: EFF_GRP_sa = 0x00000008; //Set start address of Extended group table
00000058 2108 MOV R1,#0x8
0000005A 4800 LDR R0,=0xE003C010
0000005C 6001 STR R1,[R0,#0x0]
54: ENDofTable = 0x00000008; //Set end of table address
0000005E 2108 MOV R1,#0x8
00000060 4800 LDR R0,=0xE003C014
00000062 6001 STR R1,[R0,#0x0]
55: AFMR = 0x00000000; //Enable Acceptance filters
00000064 2100 MOV R1,#0x0
00000066 4800 LDR R0,=0xE003C000
00000068 6001 STR R1,[R0,#0x0]
57: C1MOD = 0x00000000; //Release CAN controller
0000006A 2100 MOV R1,#0x0
0000006C 4800 LDR R0,=0xE0044000
0000006E 6001 STR R1,[R0,#0x0]
58: }
00000070 4770 BX R14
00000072 ENDP ; 'InitCAN1?T'
*** CODE SEGMENT '?PR?CAN1IRQ?A?CAN_RX':
61: void CAN1IRQ (void) __irq
00000000 E92D0003 STMDB R13!,{R0-R1}
64: IOCLR1 = ~C1RDA<<8; //clear output pins
00000004 E5100000 LDR R0,=0xE0044028
00000008 E5901000 LDR R1,[R0,#0x0]
0000000C E1E01001 MVN R1,R1
00000010 E1A01401 MOV R1,R1,LSL #8
00000014 E5100000 LDR R0,=0xE002801C
00000018 E5801000 STR R1,[R0,#0x0]
65: IOSET1 = C1RDA<<8; //set output pins
0000001C E5100000 LDR R0,=0xE0044028
00000020 E5901000 LDR R1,[R0,#0x0]
00000024 E1A01401 MOV R1,R1,LSL #8
00000028 E5100000 LDR R0,=0xE0028014
0000002C E5801000 STR R1,[R0,#0x0]
66: C1CMR = 0x00000004; //release the recieve buffer
00000030 E3A01004 MOV R1,#0x4
00000034 E5100000 LDR R0,=0xE0044004
00000038 E5801000 STR R1,[R0,#0x0]
67: VICVectAddr = 0x00000000; //Signal the end of interrupt
0000003C E3A01000 MOV R1,#0x0
00000040 E5100000 LDR R0,=0xFFFFF030
00000044 E5801000 STR R1,[R0,#0x0]
68: }
00000048 E8BD0003 LDMIA R13!,{R0-R1}
0000004C E25EF004 SUBS R15,R14,#0x0004
00000050 ENDP ; 'CAN1IRQ?A'
ARM COMPILER V2.00f, CAN_RX 20/02/05 14:21:05 PAGE 5
Module Information Static
----------------------------------
code size = ------
data size = 32
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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