?? main.lst
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ARM COMPILER V2.00f, main 20/02/05 10:45:52 PAGE 1
ARM COMPILER V2.00f, COMPILATION OF MODULE main
OBJECT MODULE PLACED IN main.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe main.c THUMB OPTIMIZE(7,SPEED) BROWSE DEBUG TABS(4)
stmt level source
1 /************************************************************/
2 /* PROJECT NAME: Thumb */
3 /* Project: LPC2100 Training course */
4 /* Engineer: T Martin tmartin@hitex.co.uk */
5 /* Filename: main.c */
6 /* Language: C */
7 /* Compiler: Keil ARM V2.00b */
8 /* Assembler: */
9 /* */
10 /************************************************************/
11 /* COPYRIGHT: Hitex UK Ltd 2005 */
12 /* LICENSE: THIS VERSION CREATED FOR FREE DISTRIBUTION */
13 /************************************************************/
14 /* Function: */
15 /* */
16 /* */
17 /* Demonstrates Timer 0 match interrupt and simple PWM */
18 /* modulation */
19 /* */
20 /* Oscillator frequency 12.000 Mhz */
21 /* Target board Keil MCB2100 */
22 /************************************************************/
23
24 #include <LPC21xx.H>
25
26 void T0isr(void) __irq;
27
28
29 int main(void)
30 {
31 1 VPBDIV = 0x00000002; // Configure the VPB divi
32 1
33 1 PINSEL0 |= 0x00000800; //Match1 as output
34 1 T0PR = 0x0000001E; //Load prescaler
35 1 T0TCR = 0x00000002; //Reset counter and prescaler
36 1 T0MCR = 0x00000003; //On match reset the counter and generate an interrupt
37 1 T0MR0 = 0x00000101; //Set the cycle time
38 1 T0MR1 = 0x00000000; // Set duty cycle to zero
39 1 T0EMR = 0x00000042; //On match clear MAT1
40 1 T0TCR = 0x00000001; //enable timer
41 1
42 1 VICVectAddr4 = (unsigned)T0isr; //Set the timer ISR vector address
43 1 VICVectCntl4 = 0x00000024; //Set channel
44 1 VICIntEnable |= 0x00000010; //Enable the interrupt
45 1
46 1 while(1);
47 1 }
48
49 void T0isr (void) __irq
50 {
51 1 T0EMR |= 0x00000002; //Set MAT1 high for begining of the cycle
52 1
53 1 T0MR1++; //Increment PWM Duty cycle
54 1 T0MR1 = T0MR1&0x000000FF; //Limit duty cycle
55 1
56 1 T0IR |= 0x00000001; //Clear match 0 interrupt
57 1 VICVectAddr = 0x00000000; //Dummy write to signal end of interrupt
58 1 }
ARM COMPILER V2.00f, main 20/02/05 10:45:52 PAGE 2
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC T0isr?A
PUBLIC main
*** CODE SEGMENT '?PR?main?main':
29: int main(void)
00000000 B500 PUSH {LR}
31: VPBDIV = 0x00000002; // Configure the VPB divi
00000002 2102 MOV R1,#0x2
00000004 4800 LDR R0,=0xE01FC100
00000006 7001 STRB R1,[R0,#0x0]
33: PINSEL0 |= 0x00000800; //Match1 as output
00000008 4800 LDR R2,=0x800
0000000A 4800 LDR R0,=0xE002C000
0000000C 6801 LDR R1,[R0,#0x0]
0000000E 4311 ORR R1,R2
00000010 6001 STR R1,[R0,#0x0]
34: T0PR = 0x0000001E; //Load prescaler
00000012 211E MOV R1,#0x1E
00000014 4800 LDR R0,=0xE000400C
00000016 6001 STR R1,[R0,#0x0]
35: T0TCR = 0x00000002; //Reset counter and prescaler
00000018 2102 MOV R1,#0x2
0000001A 4800 LDR R0,=0xE0004004
0000001C 6001 STR R1,[R0,#0x0]
36: T0MCR = 0x00000003; //On match reset the counter and generate an interrupt
0000001E 2103 MOV R1,#0x3
00000020 4800 LDR R0,=0xE0004014
00000022 6001 STR R1,[R0,#0x0]
37: T0MR0 = 0x00000101; //Set the cycle time
00000024 4800 LDR R1,=0x101
00000026 4800 LDR R0,=0xE0004018
00000028 6001 STR R1,[R0,#0x0]
38: T0MR1 = 0x00000000; // Set duty cycle to zero
0000002A 2100 MOV R1,#0x0
0000002C 4800 LDR R0,=0xE000401C
0000002E 6001 STR R1,[R0,#0x0]
39: T0EMR = 0x00000042; //On match clear MAT1
00000030 2142 MOV R1,#0x42
00000032 4800 LDR R0,=0xE000403C
00000034 6001 STR R1,[R0,#0x0]
40: T0TCR = 0x00000001; //enable timer
00000036 2101 MOV R1,#0x1
00000038 4800 LDR R0,=0xE0004004
0000003A 6001 STR R1,[R0,#0x0]
42: VICVectAddr4 = (unsigned)T0isr; //Set the timer ISR vector address
0000003C 4900 LDR R1,=T0isr?A ; T0isr?A
0000003E 4800 LDR R0,=0xFFFFF110
00000040 6001 STR R1,[R0,#0x0]
43: VICVectCntl4 = 0x00000024; //Set channel
00000042 2124 MOV R1,#0x24
00000044 4800 LDR R0,=0xFFFFF210
00000046 6001 STR R1,[R0,#0x0]
44: VICIntEnable |= 0x00000010; //Enable the interrupt
00000048 2210 MOV R2,#0x10
0000004A 4800 LDR R0,=0xFFFFF010
0000004C 6801 LDR R1,[R0,#0x0]
0000004E 4311 ORR R1,R2
00000050 6001 STR R1,[R0,#0x0]
46: while(1);
ARM COMPILER V2.00f, main 20/02/05 10:45:52 PAGE 3
00000052 L_1:
00000052 E7FE B L_1 ; T=0x00000052
00000054 BC08 POP {R3}
00000056 4718 BX R3
00000058 ENDP ; 'main'
*** CODE SEGMENT '?PR?T0isr?A?main':
49: void T0isr (void) __irq
00000000 E92D0003 STMDB R13!,{R0-R1}
51: T0EMR |= 0x00000002; //Set MAT1 high for begining of the cycle
00000004 E5100000 LDR R0,=0xE000403C
00000008 E5901000 LDR R1,[R0,#0x0]
0000000C E3811002 ORR R1,R1,#0x0002
00000010 E5801000 STR R1,[R0,#0x0]
53: T0MR1++; //Increment PWM Duty cycle
00000014 E5100000 LDR R0,=0xE000401C
00000018 E5901000 LDR R1,[R0,#0x0]
0000001C E2811001 ADD R1,R1,#0x0001
00000020 E5801000 STR R1,[R0,#0x0]
54: T0MR1 = T0MR1&0x000000FF; //Limit duty cycle
00000024 E5100000 LDR R0,=0xE000401C
00000028 E5901000 LDR R1,[R0,#0x0]
0000002C E20110FF AND R1,R1,#0x00FF
00000030 E5100000 LDR R0,=0xE000401C
00000034 E5801000 STR R1,[R0,#0x0]
56: T0IR |= 0x00000001; //Clear match 0 interrupt
00000038 E5100000 LDR R0,=0xE0004000
0000003C E5901000 LDR R1,[R0,#0x0]
00000040 E3811001 ORR R1,R1,#0x0001
00000044 E5801000 STR R1,[R0,#0x0]
57: VICVectAddr = 0x00000000; //Dummy write to signal end of interrupt
00000048 E3A01000 MOV R1,#0x0
0000004C E5100000 LDR R0,=0xFFFFF030
00000050 E5801000 STR R1,[R0,#0x0]
58: }
00000054 E8BD0003 LDMIA R13!,{R0-R1}
00000058 E25EF004 SUBS R15,R14,#0x0004
0000005C ENDP ; 'T0isr?A'
Module Information Static
----------------------------------
code size = ------
data size = ------
const size = ------
End of Module Information.
ARM COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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