?? p30f2010.h
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/*-------------------------------------------------------------------------
*
* MPLAB-C30 dsPIC30F2010 processor header
*
* (c) Copyright 2005-2006 Microchip Technology, All rights reserved
*
* File Description / Notes:
* =========================
* 1] This header file defines special function registers (SFR), and useful
* macros for the dsPIC30Fxxxx Family of Digital Signal
* Controllers (also referred to as the dsPIC).
* 2] The register and bit names used in this file match the
* dsPIC30Fxxxx data sheets as closely as possible.
* 3] The memory locations of the registers defined in this header file are
* specified in the respective linker scripts.
* 4] SFR definitions are listed in the ascending order of memory addresses
* and are grouped based on the module they belong to. For e.g., WREG10
* is listed before ACCAL, and the Core SFRs are grouped separately
* from the Interrupt Controller SFRs or the General Purpose Timer SFRs.
*
* Revision History:
* =================
* --------------------------------------------------------------------------
* Rev: Date: Details: Who:
* --------------------------------------------------------------------------
* 2.0 23 Apr 2003 New file P Sinha
* 2.0a 24 Apr 2003 Added CEID bit P Sinha
* 2.0b 30 Apr 2003 Removed suffix 'B' from device number P Sinha
* 2.2 17 Jun 2003 Renamed CONV bit to DONE P Sinha
* 2.3 20 Jun 2003 Corrections in Config Fuses comments P Sinha
* 2.3b 5 Aug 2003 Added TUN1-4 bits in OSCCON P Sinha
* 2.3c 18 Sep 2003 DFLTCON changes P Sinha
* 2.4 10 Oct 2003 Added macros for data allocation and ISRs P Sinha
* 2.5 25 Nov 2003 Renamed TUN1-4 bits to TUNF0-3 P Sinha
* 3.0 30 Mar 2004 Added defines for unique SFR bit names P Sinha
* 3.1 5 Apr 2004 Added underscore before SFR bit labels P Sinha
* 3.2 11 Apr 2004 Enhanced config macro usage examples P Sinha
* 3.3 14 Apr 2004 Corrected a typo in the _U1RXIE bit label P Sinha
* 4.0 28 Sep 2004 Changed data allocation macro definitions P Sinha
* 4.1 22 Dec 2004 Corrected a typo in the _U1RXIE definition P Sinha
* 4.1a 14 Mar 2005 Removed LVD definitions P Sinha
* 4.2 4 Apr 2005 Renamed EC_IO to ECIO and ERC_IO to ERCIO P Sinha
* 4.2a 27 Jun 2005 Fixed typos in comments regarding macros G McCar
* 4.3 1 Jul 2005 Updated section syntax in config macros P Sinha
* 4.4 12 Aug 2005 Changed FGS to match silicon H Vasuki
* 4.4a 06 Oct 2005 reversed previous change to FGS for 30F2010 H Vasuki
* v3.00 02 Feb 2007 Added processor check S Curtis
* (Rev reflects compiler version)
* --------------------------------------------------------------------------
*
* ------------------------------------------------------------------------*/
#ifndef __dsPIC30F2010__
#error "Include file does not match processor setting"
#endif
#ifndef __30F2010_H
#define __30F2010_H
/* ------------------------- */
/* Core Register Definitions */
/* ------------------------- */
/* W registers W0-W15 */
extern volatile unsigned int WREG0 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG1 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG2 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG3 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG4 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG5 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG6 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG7 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG8 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG9 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG10 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG11 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG12 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG13 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG14 __attribute__((__sfr__,__deprecated__,__unsafe__));
extern volatile unsigned int WREG15 __attribute__((__sfr__,__deprecated__,__unsafe__));
/* SPLIM: Stack Pointer Limit */
extern volatile unsigned int SPLIM __attribute__((__sfr__));
/* Alternative access structure for the 40-bit accumulators */
typedef struct tagACC {
unsigned int L;
unsigned int H;
unsigned char U;
} ACC;
/* Acc A<15:0> */
extern volatile unsigned int ACCAL __attribute__((__sfr__));
/* Acc A<31:16> */
extern volatile unsigned int ACCAH __attribute__((__sfr__));
/* Acc A<39:32> */
extern volatile unsigned char ACCAU __attribute__((__sfr__));
/* Acc A defined as a structure consisting of the 3 parts */
extern volatile ACC ACCA __attribute__((__sfr__));
/* Acc B<15:0> */
extern volatile unsigned int ACCBL __attribute__((__sfr__));
/* Acc B<31:16> */
extern volatile unsigned int ACCBH __attribute__((__sfr__));
/* Acc B<39:32> */
extern volatile unsigned char ACCBU __attribute__((__sfr__));
/* Acc B defined as a structure consisting of the 3 parts */
extern volatile ACC ACCB __attribute__((__sfr__));
/* PCL: Program Counter low word */
extern volatile unsigned int PCL __attribute__((__sfr__));
/* PCH: Program Counter high byte */
extern volatile unsigned char PCH __attribute__((__sfr__));
/* TBLPAG: Table Page Register */
extern volatile unsigned char TBLPAG __attribute__((__sfr__));
/* PSVPAG: Program Space Visibility Page Register */
extern volatile unsigned char PSVPAG __attribute__((__sfr__));
/* RCOUNT: REPEAT loop count */
extern volatile unsigned int RCOUNT __attribute__((__sfr__));
/* DCOUNT: DO loop count */
extern volatile unsigned int DCOUNT __attribute__((__sfr__));
/* DOSTARTL: DO loop start address bits <15:0> */
extern volatile unsigned int DOSTARTL __attribute__((__sfr__));
/* DOSTARTH: DO loop start address bits <23:16> */
extern volatile unsigned int DOSTARTH __attribute__((__sfr__));
/* DOENDL: DO loop end address bits <15:0> */
extern volatile unsigned int DOENDL __attribute__((__sfr__));
/* DOENDH: DO loop end address bits <23:16> */
extern volatile unsigned int DOENDH __attribute__((__sfr__));
/* SR: Status Register */
extern volatile unsigned int SR __attribute__((__sfr__));
typedef struct tagSRBITS {
unsigned C :1; /* Carry flag */
unsigned Z :1; /* Sticky Zero flag */
unsigned OV :1; /* Overflow flag */
unsigned N :1; /* Negative flag */
unsigned RA :1; /* REPEAT loop active flag */
unsigned IPL :3; /* CPU Interrupt Priority Level */
unsigned DC :1; /* Digit Carry flag */
unsigned DA :1; /* DO loop active flag */
unsigned SAB :1; /* Combined A/B saturation flag */
unsigned OAB :1; /* Combined A/B overflow flag */
unsigned SB :1; /* Acc B saturation flag */
unsigned SA :1; /* Acc A saturation flag */
unsigned OB :1; /* Acc B overflow flag */
unsigned OA :1; /* Acc A overflow flag */
} SRBITS;
extern volatile SRBITS SRbits __attribute__((__sfr__));
/* CORCON: CPU Mode control Register */
extern volatile unsigned int CORCON __attribute__((__sfr__));
typedef struct tagCORCONBITS {
unsigned IF :1; /* Integer/Fractional mode */
unsigned RND :1; /* Rounding mode */
unsigned PSV :1; /* Program Space Visibility enable */
unsigned IPL3 :1; /* CPU Interrupt Priority Level bit 3 */
unsigned ACCSAT :1; /* Acc saturation mode */
unsigned SATDW :1; /* Data space write saturation enable */
unsigned SATB :1; /* Acc B saturation enable */
unsigned SATA :1; /* Acc A saturation enable */
unsigned DL :3; /* DO loop nesting level status */
unsigned EDT :1; /* Early DO loop termination control */
unsigned US :1; /* Signed/Unsigned mode */
unsigned :3;
} CORCONBITS;
extern volatile CORCONBITS CORCONbits __attribute__((__sfr__));
/* MODCON: Modulo Addressing Control Register */
extern volatile unsigned int MODCON __attribute__((__sfr__));
typedef struct tagMODCONBITS {
unsigned XWM :4; /* X-RAGU/X-WAGU modulo addressing register select */
unsigned YWM :4; /* Y-RAGU modulo addressing register select */
unsigned BWM :4; /* Bit-reversed addressing register select */
unsigned :2;
unsigned YMODEN :1; /* Y-RAGU modulo addressing enable */
unsigned XMODEN :1; /* X-RAGU/X-WAGU modulo addressing enable */
} MODCONBITS;
extern volatile MODCONBITS MODCONbits __attribute__((__sfr__));
/* XMODSRT: X-RAGU/X-WAGU modulo buffer start address */
extern volatile unsigned int XMODSRT __attribute__((__sfr__));
/* XMODEND: X-RAGU/X-WAGU modulo buffer end address */
extern volatile unsigned int XMODEND __attribute__((__sfr__));
/* YMODSRT: Y-RAGU modulo buffer start address */
extern volatile unsigned int YMODSRT __attribute__((__sfr__));
/* YMODEND: Y-RAGU modulo buffer end address */
extern volatile unsigned int YMODEND __attribute__((__sfr__));
/* XBREV: X-WAGU Bit-reversed Addressing Control Register */
extern volatile unsigned int XBREV __attribute__((__sfr__));
typedef struct tagXBREVBITS {
unsigned XB :15; /* Bit-reversed addressing register select */
unsigned BREN :1; /* Bit-reversed addressing enable */
} XBREVBITS;
extern volatile XBREVBITS XBREVbits __attribute__((__sfr__));
/* DISICNT: Disable Interrupt Cycle Count */
extern volatile unsigned int DISICNT __attribute__((__sfr__));
typedef struct tagDISICNTBITS {
unsigned DISICNT:14;
unsigned :2;
} DISICNTBITS;
extern volatile DISICNTBITS DISICNTbits __attribute__((__sfr__));
/* ----------------------------------------- */
/* Interrupt Controller register definitions */
/* ----------------------------------------- */
/* INTCON1: Interrupt Control Register 1 */
extern volatile unsigned int INTCON1 __attribute__((__sfr__));
typedef struct tagINTCON1BITS {
unsigned :1;
unsigned OSCFAIL:1;
unsigned STKERR :1;
unsigned ADDRERR:1;
unsigned MATHERR:1;
unsigned :3;
unsigned COVTE :1;
unsigned OVBTE :1;
unsigned OVATE :1;
unsigned :4;
unsigned NSTDIS :1;
} INTCON1BITS;
extern volatile INTCON1BITS INTCON1bits __attribute__((__sfr__));
/* INTCON2: Interrupt Control Register 2 */
extern volatile unsigned int INTCON2 __attribute__((__sfr__));
typedef struct tagINTCON2BITS {
unsigned INT0EP :1;
unsigned INT1EP :1;
unsigned INT2EP :1;
unsigned :11;
unsigned DISI :1;
unsigned ALTIVT :1;
} INTCON2BITS;
extern volatile INTCON2BITS INTCON2bits __attribute__((__sfr__));
/* IFS0: Interrupt Flag Status Register 0 */
extern volatile unsigned int IFS0 __attribute__((__sfr__));
typedef struct tagIFS0BITS {
unsigned INT0IF :1;
unsigned IC1IF :1;
unsigned OC1IF :1;
unsigned T1IF :1;
unsigned IC2IF :1;
unsigned OC2IF :1;
unsigned T2IF :1;
unsigned T3IF :1;
unsigned SPI1IF :1;
unsigned U1RXIF :1;
unsigned U1TXIF :1;
unsigned ADIF :1;
unsigned NVMIF :1;
unsigned SI2CIF :1;
unsigned MI2CIF :1;
unsigned CNIF :1;
} IFS0BITS;
extern volatile IFS0BITS IFS0bits __attribute__((__sfr__));
/* IFS1: Interrupt Flag Status Register 1 */
extern volatile unsigned int IFS1 __attribute__((__sfr__));
typedef struct tagIFS1BITS {
unsigned INT1IF :1;
unsigned IC7IF :1;
unsigned IC8IF :1;
unsigned :4;
unsigned INT2IF :1;
unsigned :8;
} IFS1BITS;
extern volatile IFS1BITS IFS1bits __attribute__((__sfr__));
/* IFS2: Interrupt Flag Status Register 2 */
extern volatile unsigned int IFS2 __attribute__((__sfr__));
typedef struct tagIFS2BITS {
unsigned :7;
unsigned PWMIF :1;
unsigned QEIIF :1;
unsigned :2;
unsigned FLTAIF :1;
unsigned FLTBIF :1;
unsigned :3;
} IFS2BITS;
extern volatile IFS2BITS IFS2bits __attribute__((__sfr__));
/* IEC0: Interrupt Enable Control Register 0 */
extern volatile unsigned int IEC0 __attribute__((__sfr__));
typedef struct tagIEC0BITS {
unsigned INT0IE :1;
unsigned IC1IE :1;
unsigned OC1IE :1;
unsigned T1IE :1;
unsigned IC2IE :1;
unsigned OC2IE :1;
unsigned T2IE :1;
unsigned T3IE :1;
unsigned SPI1IE :1;
unsigned U1RXIE :1;
unsigned U1TXIE :1;
unsigned ADIE :1;
unsigned NVMIE :1;
unsigned SI2CIE :1;
unsigned MI2CIE :1;
unsigned CNIE :1;
} IEC0BITS;
extern volatile IEC0BITS IEC0bits __attribute__((__sfr__));
/* IEC1: Interrupt Enable Control Register 1 */
extern volatile unsigned int IEC1 __attribute__((__sfr__));
typedef struct tagIEC1BITS {
unsigned INT1IE :1;
unsigned IC7IE :1;
unsigned IC8IE :1;
unsigned :4;
unsigned INT2IE :1;
unsigned :8;
} IEC1BITS;
extern volatile IEC1BITS IEC1bits __attribute__((__sfr__));
/* IEC2: Interrupt Enable Control Register 2 */
extern volatile unsigned int IEC2 __attribute__((__sfr__));
typedef struct tagIEC2BITS {
unsigned :7;
unsigned PWMIE :1;
unsigned QEIIE :1;
unsigned :2;
unsigned FLTAIE :1;
unsigned FLTBIE :1;
unsigned :3;
} IEC2BITS;
extern volatile IEC2BITS IEC2bits __attribute__((__sfr__));
/* IPC0: Interrupt Priority Control Register 0 */
extern volatile unsigned int IPC0 __attribute__((__sfr__));
typedef struct tagIPC0BITS {
unsigned INT0IP :3;
unsigned :1;
unsigned IC1IP :3;
unsigned :1;
unsigned OC1IP :3;
unsigned :1;
unsigned T1IP :3;
unsigned :1;
} IPC0BITS;
extern volatile IPC0BITS IPC0bits __attribute__((__sfr__));
/* IPC1: Interrupt Priority Control Register 1 */
extern volatile unsigned int IPC1 __attribute__((__sfr__));
typedef struct tagIPC1BITS {
unsigned IC2IP :3;
unsigned :1;
unsigned OC2IP :3;
unsigned :1;
unsigned T2IP :3;
unsigned :1;
unsigned T3IP :3;
unsigned :1;
} IPC1BITS;
extern volatile IPC1BITS IPC1bits __attribute__((__sfr__));
/* IPC2: Interrupt Priority Control Register 2 */
extern volatile unsigned int IPC2 __attribute__((__sfr__));
typedef struct tagIPC2BITS {
unsigned SPI1IP :3;
unsigned :1;
unsigned U1RXIP :3;
unsigned :1;
unsigned U1TXIP :3;
unsigned :1;
unsigned ADIP :3;
unsigned :1;
} IPC2BITS;
extern volatile IPC2BITS IPC2bits __attribute__((__sfr__));
/* IPC3: Interrupt Priority Control Register 3 */
extern volatile unsigned int IPC3 __attribute__((__sfr__));
typedef struct tagIPC3BITS {
unsigned NVMIP :3;
unsigned :1;
unsigned SI2CIP :3;
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