?? p30f2010.h
字號:
unsigned :1;
unsigned MI2CIP :3;
unsigned :1;
unsigned CNIP :3;
unsigned :1;
} IPC3BITS;
extern volatile IPC3BITS IPC3bits __attribute__((__sfr__));
/* IPC4: Interrupt Priority Control Register 4 */
extern volatile unsigned int IPC4 __attribute__((__sfr__));
typedef struct tagIPC4BITS {
unsigned INT1IP :3;
unsigned :1;
unsigned IC7IP :3;
unsigned :1;
unsigned IC8IP :3;
unsigned :5;
} IPC4BITS;
extern volatile IPC4BITS IPC4bits __attribute__((__sfr__));
/* IPC5: Interrupt Priority Control Register 5 */
extern volatile unsigned int IPC5 __attribute__((__sfr__));
typedef struct tagIPC5BITS {
unsigned :12;
unsigned INT2IP :3;
unsigned :1;
} IPC5BITS;
extern volatile IPC5BITS IPC5bits __attribute__((__sfr__));
/* IPC9: Interrupt Priority Control Register 9 */
extern volatile unsigned int IPC9 __attribute__((__sfr__));
typedef struct tagIPC9BITS {
unsigned :12;
unsigned PWMIP :3;
unsigned :1;
} IPC9BITS;
extern volatile IPC9BITS IPC9bits __attribute__((__sfr__));
/* IPC10: Interrupt Priority Control Register 10 */
extern volatile unsigned int IPC10 __attribute__((__sfr__));
typedef struct tagIPC10BITS {
unsigned QEIIP :3;
unsigned :9;
unsigned FLTAIP :3;
unsigned :1;
} IPC10BITS;
extern volatile IPC10BITS IPC10bits __attribute__((__sfr__));
/* IPC11: Interrupt Priority Control Register 11 */
extern volatile unsigned int IPC11 __attribute__((__sfr__));
typedef struct tagIPC11BITS {
unsigned FLTBIP :3;
unsigned :13;
} IPC11BITS;
extern volatile IPC11BITS IPC11bits __attribute__((__sfr__));
/* INTTREG: Interrupt Controller Test Register */
extern volatile unsigned int INTTREG __attribute__((__sfr__));
typedef struct tagINTTREGBITS {
unsigned VECNUM :6;
unsigned :2;
unsigned ILR :4;
unsigned :1;
unsigned VHOLD :1;
unsigned TMODE :1;
unsigned IRQTOCPU:1;
} INTTREGBITS;
extern volatile INTTREGBITS INTTREGbits __attribute__((__sfr__));
/* ---------------------------------------------- */
/* Input Change Notification register definitions */
/* ---------------------------------------------- */
/* CNEN1: Input Change Notification Interrupt Enable Register 1 */
extern volatile unsigned int CNEN1 __attribute__((__sfr__));
typedef struct tagCNEN1BITS {
unsigned CN0IE :1;
unsigned CN1IE :1;
unsigned CN2IE :1;
unsigned CN3IE :1;
unsigned CN4IE :1;
unsigned CN5IE :1;
unsigned CN6IE :1;
unsigned CN7IE :1;
unsigned CN8IE :1;
unsigned CN9IE :1;
unsigned CN10IE :1;
unsigned CN11IE :1;
unsigned CN12IE :1;
unsigned CN13IE :1;
unsigned CN14IE :1;
unsigned CN15IE :1;
} CNEN1BITS;
extern volatile CNEN1BITS CNEN1bits __attribute__((__sfr__));
/* CNEN2: Input Change Notification Interrupt Enable Register 2 */
extern volatile unsigned int CNEN2 __attribute__((__sfr__));
typedef struct tagCNEN2BITS {
unsigned CN16IE :1;
unsigned CN17IE :1;
unsigned CN18IE :1;
unsigned CN19IE :1;
unsigned CN20IE :1;
unsigned CN21IE :1;
unsigned :10;
} CNEN2BITS;
extern volatile CNEN2BITS CNEN2bits __attribute__((__sfr__));
/* CNPU1: Input Change Notification Pullup Enable Register 1 */
extern volatile unsigned int CNPU1 __attribute__((__sfr__));
typedef struct tagCNPU1BITS {
unsigned CN0PUE :1;
unsigned CN1PUE :1;
unsigned CN2PUE :1;
unsigned CN3PUE :1;
unsigned CN4PUE :1;
unsigned CN5PUE :1;
unsigned CN6PUE :1;
unsigned CN7PUE :1;
unsigned CN8PUE :1;
unsigned CN9PUE :1;
unsigned CN10PUE:1;
unsigned CN11PUE:1;
unsigned CN12PUE:1;
unsigned CN13PUE:1;
unsigned CN14PUE:1;
unsigned CN15PUE:1;
} CNPU1BITS;
extern volatile CNPU1BITS CNPU1bits __attribute__((__sfr__));
/* CNPU2: Input Change Notification Pullup Enable Register 2 */
extern volatile unsigned int CNPU2 __attribute__((__sfr__));
typedef struct tagCNPU2BITS {
unsigned CN16PUE:1;
unsigned CN17PUE:1;
unsigned CN18PUE:1;
unsigned CN19PUE:1;
unsigned CN20PUE:1;
unsigned CN21PUE:1;
unsigned :10;
} CNPU2BITS;
extern volatile CNPU2BITS CNPU2bits __attribute__((__sfr__));
/* --------------------------- */
/* Timer1 register definitions */
/* --------------------------- */
/* Generic structure for Timer 1 Control Register */
typedef struct tagTCON_16BIT {
unsigned :1;
unsigned TCS :1;
unsigned TSYNC :1;
unsigned :1;
unsigned TCKPS :2;
unsigned TGATE :1;
unsigned :6;
unsigned TSIDL :1;
unsigned :1;
unsigned TON :1;
} TCON_16BIT;
/* TMR1: Timer 1 Count Register */
extern volatile unsigned int TMR1 __attribute__((__sfr__));
/* PR1: Timer 1 Period Register */
extern volatile unsigned int PR1 __attribute__((__sfr__));
/* T1CON: Timer 1 Control Register */
extern volatile unsigned int T1CON __attribute__((__sfr__));
extern volatile TCON_16BIT T1CONbits __attribute__((__sfr__));
/* ----------------------------- */
/* Timer2/3 register definitions */
/* ----------------------------- */
/* Generic structure for Timer 2 and Timer 4 Control Registers */
typedef struct tagTCON_EVEN {
unsigned :1;
unsigned TCS :1;
unsigned :1;
unsigned T32 :1;
unsigned TCKPS :2;
unsigned TGATE :1;
unsigned :6;
unsigned TSIDL :1;
unsigned :1;
unsigned TON :1;
} TCON_EVEN;
/* Generic structure for Timer 3 and Timer 5 Control Registers */
typedef struct tagTCON_ODD {
unsigned :1;
unsigned TCS :1;
unsigned :2;
unsigned TCKPS :2;
unsigned TGATE :1;
unsigned :6;
unsigned TSIDL :1;
unsigned :1;
unsigned TON :1;
} TCON_ODD;
/* TMR2: Timer 2 Count Register */
extern volatile unsigned int TMR2 __attribute__((__sfr__));
/* TMR3HLD: Timer 3 Holding Register */
extern volatile unsigned int TMR3HLD __attribute__((__sfr__));
/* TMR3: Timer 3 Count Register */
extern volatile unsigned int TMR3 __attribute__((__sfr__));
/* PR2: Timer 2 Period Register */
extern volatile unsigned int PR2 __attribute__((__sfr__));
/* PR3: Timer 3 Period Register */
extern volatile unsigned int PR3 __attribute__((__sfr__));
/* T2CON: Timer 2 Control Register */
extern volatile unsigned int T2CON __attribute__((__sfr__));
extern volatile TCON_EVEN T2CONbits __attribute__((__sfr__));
/* T3CON: Timer 3 Control Register */
extern volatile unsigned int T3CON __attribute__((__sfr__));
extern volatile TCON_ODD T3CONbits __attribute__((__sfr__));
/* ------------------------------------------------- */
/* Quadrature Encoder Interface register definitions */
/* ------------------------------------------------- */
/* QEICON: QEI Control Register */
extern volatile unsigned int QEICON __attribute__((__sfr__));
typedef struct tagQEICONBITS {
unsigned UPDN_SRC:1;
unsigned TQCS :1;
unsigned POSRES :1;
unsigned TQCKPS :2;
unsigned TQGATE :1;
unsigned PCDOUT :1;
unsigned SWPAB :1;
unsigned QEIM :3;
unsigned UPDN :1;
unsigned INDX :1;
unsigned QEISIDL:1;
unsigned :1;
unsigned CNTERR :1;
} QEICONBITS;
extern volatile QEICONBITS QEICONbits __attribute__((__sfr__));
/* DFLTCON: Digital Filter Control Register */
extern volatile unsigned int DFLTCON __attribute__((__sfr__));
typedef struct tagDFLTCONBITS {
unsigned :4;
unsigned QECK :3;
unsigned QEOUT :1;
unsigned CEID :1;
unsigned IMV :2;
unsigned :5;
} DFLTCONBITS;
extern volatile DFLTCONBITS DFLTCONbits __attribute__((__sfr__));
/* POSCNT: Position Counter Register */
extern volatile unsigned int POSCNT __attribute__((__sfr__));
/* MAXCNT: Maximum Count Register */
extern volatile unsigned int MAXCNT __attribute__((__sfr__));
/* ---------------------------------- */
/* Input Capture register definitions */
/* ---------------------------------- */
/* Generic structure of entire SFR area for each Input Capture module */
typedef struct tagIC {
unsigned int icxbuf;
unsigned int icxcon;
} IC, *PIC;
/* SFR blocks for each Input Capture module */
extern volatile IC IC1 __attribute__((__sfr__));
extern volatile IC IC2 __attribute__((__sfr__));
extern volatile IC IC7 __attribute__((__sfr__));
extern volatile IC IC8 __attribute__((__sfr__));
/* Generic structure for Input Capture Control Registers */
typedef struct tagICxCONBITS {
unsigned ICM :3;
unsigned ICBNE :1;
unsigned ICOV :1;
unsigned ICI :2;
unsigned ICTMR :1;
unsigned :5;
unsigned ICSIDL :1;
unsigned :2;
} ICxCONBITS;
/* IC1BUF: Input Capture 1 Buffer */
extern volatile unsigned int IC1BUF __attribute__((__sfr__));
/* IC1CON: Input Capture 1 Control Register */
extern volatile unsigned int IC1CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC1CONbits __attribute__((__sfr__));
/* IC2BUF: Input Capture 2 Buffer */
extern volatile unsigned int IC2BUF __attribute__((__sfr__));
/* IC2CON: Input Capture 2 Control Register */
extern volatile unsigned int IC2CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC2CONbits __attribute__((__sfr__));
/* IC7BUF: Input Capture 7 Buffer */
extern volatile unsigned int IC7BUF __attribute__((__sfr__));
/* IC7CON: Input Capture 7 Control Register */
extern volatile unsigned int IC7CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC7CONbits __attribute__((__sfr__));
/* IC8BUF: Input Capture 8 Buffer */
extern volatile unsigned int IC8BUF __attribute__((__sfr__));
/* IC8CON: Input Capture 8 Control Register */
extern volatile unsigned int IC8CON __attribute__((__sfr__));
extern volatile ICxCONBITS IC8CONbits __attribute__((__sfr__));
/* --------------------------------------- */
/* Output Compare/PWM register definitions */
/* --------------------------------------- */
/* Generic structure of entire SFR area for each Output Compare module */
typedef struct tagOC {
unsigned int ocxrs;
unsigned int ocxr;
unsigned int ocxcon;
} OC, *POC;
/* SFR blocks for each Output Compare module */
extern volatile OC OC1 __attribute__((__sfr__));
extern volatile OC OC2 __attribute__((__sfr__));
/* Generic structure for Output Compare Control Registers */
typedef struct tagOCxCONBITS {
unsigned OCM :3;
unsigned OCTSEL :1;
unsigned OCFLT :1;
unsigned :8;
unsigned OCSIDL :1;
unsigned :2;
} OCxCONBITS;
/* OC1RS: Output Compare 1 Secondary Register */
extern volatile unsigned int OC1RS __attribute__((__sfr__));
/* OC1R: Output Compare 1 Main Register */
extern volatile unsigned int OC1R __attribute__((__sfr__));
/* OC1CON: Output Compare 1 Control Register */
extern volatile unsigned int OC1CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC1CONbits __attribute__((__sfr__));
/* OC2RS: Output Compare 2 Secondary Register */
extern volatile unsigned int OC2RS __attribute__((__sfr__));
/* OC2R: Output Compare 2 Main Register */
extern volatile unsigned int OC2R __attribute__((__sfr__));
/* OC2CON: Output Compare 2 Control Register */
extern volatile unsigned int OC2CON __attribute__((__sfr__));
extern volatile OCxCONBITS OC2CONbits __attribute__((__sfr__));
/* -------------------------------------- */
/* Motor Control PWM register definitions */
/* -------------------------------------- */
/* PTCON: PWM Timerbase Control Register */
extern volatile unsigned int PTCON __attribute__((__sfr__));
typedef struct tagPTCONBITS {
unsigned PTMOD :2;
unsigned PTCKPS :2;
unsigned PTOPS :4;
unsigned :5;
unsigned PTSIDL :1;
unsigned :1;
unsigned PTEN :1;
} PTCONBITS;
extern volatile PTCONBITS PTCONbits __attribute__((__sfr__));
/* PTMR: PWM Timebase Count Register */
extern volatile unsigned int PTMR __attribute__((__sfr__));
typedef struct tagPTMRBITS {
unsigned PTMR :15;
unsigned PTDIR :1;
} PTMRBITS;
extern volatile PTMRBITS PTMRbits __attribute__((__sfr__));
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