www.pudn.com > src.rar > ddi_display_controller_HX8347A.c
 

   1. ////////////////////////////////////////////////////////////////////////////////   
   2. //! \addtogroup ddi_display   
   3. //! @{   
   4. //   
   5. // Copyright (c) 2004-2005 SigmaTel, Inc.   
   6. //   
   7. //! \file ddi_display_controller_ssd1289.c   
   8. //! \brief Structures and code specific to the Solomon Systech 1289 controller   
   9. //! \date 03/2006   
  10. //!   
  11. ////////////////////////////////////////////////////////////////////////////////   
  12. ////////////////////////////////////////////////////////////////////////////////   
  13. // Includes and external references   
  14. ////////////////////////////////////////////////////////////////////////////////   
  15. #include <types.h>   
  16. #include <drivers\ddi_display.h>   
  17. #include <stdarg.h>   
  18. #include <registers\regspower.h>  // need this to check for alkaline battery    
  19. #include <registers\hw_irq.h>   
  20. #include "..\ddi_display_controller.h"   
  21. #include <components\gfx.h>   
  22. #include <hw\hw_lcdif.h>   
  23. #include <hw\hw_gpio.h>   
  24. #include <drivers\ddi_gpio.h>   
  25. #include <drivers\ddi_pwm.h>   
  26. #include <drivers\ddi_lcdif.h>   
  27. #include <drivers\ddi_icoll.h>   
  28. #include <string.h>   
  29. #if defined(RTOS_THREADX)   
  30. #include <os\os_thi_api.h>   
  31. #endif   
  32. #include <registers\regspwm.h>   
  33. #include <registers\regspinctrl.h>   
  34. #include <hw\vmemory.h>   
  35. #include <interrupts.h>   
  36. #include <drivers\ddi_etm.h>   
  37.    
  38. #include <drivers\ddi_rtc.h>   
  39. ////////////////////////////////////////////////////////////////////////////////   
  40. // Externs   
  41. ////////////////////////////////////////////////////////////////////////////////   
  42. ddi_display_Rotation_t g_ddi_display_eRotation = DDI_DISPLAY_ROTATION_NONE;   
  43. gfx_BitmapTypeEnum_t g_ddi_display_eBitmapType = BITMAP_TYPE_16BPP_565;   
  44.    
  45. #if defined(RTOS_THREADX)   
  46. //! Handler for the DMA completion callback   
  47. extern void g_ddi_display_DmaCompletionCallback(void *);   
  48. #endif   
  49.    
  50.    
  51. ////////////////////////////////////////////////////////////////////////////////   
  52. // Definitions   
  53. ////////////////////////////////////////////////////////////////////////////////   
  54.    
  55. // 16bit interface for TopSun   
  56. #define DDI_LCDIF_WORDLENGTH_16BITS 1   
  57.    
  58. #ifndef DDI_DISPLAY_BACKLIGHT_PWM_CHANNEL   
  59. #define DDI_DISPLAY_BACKLIGHT_PWM_CHANNEL 2   
  60. #endif   
  61.    
  62. #ifndef DDI_DISPLAY_DATA_SETUP_XCLKS    
  63. #define DDI_DISPLAY_DATA_SETUP_XCLKS 1   
  64. #endif   
  65.    
  66. #ifndef DDI_DISPLAY_DATA_HOLD_XCLKS   
  67. #define DDI_DISPLAY_DATA_HOLD_XCLKS  1   
  68. #endif   
  69.    
  70. #ifndef DDI_DISPLAY_CMD_SETUP_XCLKS    
  71. #define DDI_DISPLAY_CMD_SETUP_XCLKS  1   
  72. #endif   
  73.    
  74. #ifndef DDI_DISPLAY_CMD_HOLD_XCLKS    
  75. #define DDI_DISPLAY_CMD_HOLD_XCLKS   1   
  76. #endif   
  77.    
  78. #ifndef DDI_DISPLAY_DEFAULT_SIZE_HORIZONTAL    
  79. #define DDI_DISPLAY_DEFAULT_SIZE_HORIZONTAL 320   
  80. #endif   
  81.    
  82. #ifndef DDI_DISPLAY_DEFAULT_SIZE_VERTICAL   
  83. #define DDI_DISPLAY_DEFAULT_SIZE_VERTICAL 240   
  84. #endif   
  85.    
  86. //! Min allowed brightness percentage   
  87. #define MIN_BRIGHTNESS_PERCENTAGE 0   
  88. //! Alkaline batttery can't support the power needed for high brightness   
  89. #define ALKALINE_MIN_BRIGHTNESS_PERCENTAGE 10   
  90.    
  91. //! Max allowed brightness percentage   
  92. #define MAX_BRIGHTNESS_PERCENTAGE 81   
  93. //! Alkaline batttery can't support the power needed for high brightness   
  94. #define ALKALINE_MAX_BRIGHTNESS_PERCENTAGE 20   
  95.    
  96.    
  97. //! Defines the CDIV value for OS independent PWM control   
  98. #define BACKLIGHT_PWM_CDIV BV_PWMn_PERIOD_CDIV__DIV_64   
  99. //! Defines the period in divided clocks for OS independent PWM control   
 100. #define BACKLIGHT_PWM_PERIOD 200   
 101.    
 102. // When the controller is using the LCDIF in 16bit bus mode, command bytes   
 103. // cannot be sent in a packed 16 bit word transfer.  Each command byte must    
 104. // be in its own 16-bit word transfer.  Furthermore, the command byte has to   
 105. // in the lower byte of the 16-bit word.  In 16bit mode, 2 command bytes   
 106. // cannot be packed into 1 16-bit word.   
 107. #ifdef DDI_LCDIF_WORDLENGTH_16BITS   
 108. #define DDI_DISPLAY_WORD_TYPE uint16_t   
 109. #define DDI_DISPLAY_WORDLENGTH WORDLENGTH_16BITS   
 110. #define DDI_DISPLAY_DATA_SWIZZLE NO_SWAP   
 111. #else   
 112. #define DDI_DISPLAY_WORD_TYPE uint8_t   
 113. #define DDI_DISPLAY_WORDLENGTH WORDLENGTH_8BITS   
 114. #define DDI_DISPLAY_DATA_SWIZZLE HWD_BYTE_SWAP    
 115. #endif   
 116.    
 117. // Max width for the controller   
 118. #define DDI_DISPLAY_CONTROLLER_MAX_WIDTH 320   
 119.    
 120. // Max height for the controller   
 121. #define DDI_DISPLAY_CONTROLLER_MAX_HEIGHT 240   
 122.    
 123. // Max bytes per pixel   
 124. #define DDI_DISPLAY_CONTROLLER_MAX_BYTES_PER_PIXEL 2   
 125.    
 126. //! Specifies how many DMA descriptors are allocated for the display driver.   
 127. //! This will determine the maximum size of the frame buffer that can be   
 128. //! transferred with one DMA transaction.  Each DMA descriptor is limited to   
 129. //! 64k bytes of data.   
 130. #define NUM_DMA_DESCRIPTORS (1 + \   
 131.     ((DDI_DISPLAY_CONTROLLER_MAX_WIDTH * DDI_DISPLAY_CONTROLLER_MAX_HEIGHT * \   
 132.      DDI_DISPLAY_CONTROLLER_MAX_BYTES_PER_PIXEL) / (64 * 1024)))    
 133.    
 134. //! Gpio configuration for video mode operation   
 135. #define GPIO_VSYNC_CONFIG_MASK (GPIO_MASK_SEL3 | GPIO_MASK_INPUT | GPIO_MASK_IRQ_RISING)   
 136.    
 137. //! Interrupt vector for VSYNC   
 138. #define GPIO_VSYNC_IRQ_VECTOR VECTOR_IRQ_GPIO1   
 139.    
 140. //! VSYNC interrupt enable/disable bit   
 141. #define GPIO_VSYNC_IRQ_BIT (0x00200000) // Bit 21 in GPIO bank 1 (LCD_BUSY)   
 142.    
 143. //! VSYNC interrupt pin   
 144. #define GPIO_VSYNC_IRQ_PIN LCD_BUSY   
 145.    
 146. //! Macro to enable the VSYNC interrupt   
 147. #define ENABLE_VSYNC_IRQ() HW_PINCTRL_PIN2IRQ1_SET(GPIO_VSYNC_IRQ_BIT) //HW_PINCTRL_IRQEN1_SET(GPIO_VSYNC_IRQ_BIT)   
 148.    
 149. //! Macro to disable the VSYNC interrupt   
 150. #define DISABLE_VSYNC_IRQ() HW_PINCTRL_PIN2IRQ1_CLR(GPIO_VSYNC_IRQ_BIT) //HW_PINCTRL_IRQEN1_CLR(GPIO_VSYNC_IRQ_BIT)   
 151.    
 152. //! Macro to check if the VSYNC IRQ status bit is set   
 153. #define CHECK_VSYNC_IRQ_STATUS() ( HW_PINCTRL_IRQSTAT1_RD() & GPIO_VSYNC_IRQ_BIT )   
 154.    
 155. //! Macro to clear the VSYNC IRQ status   
 156. #define CLEAR_VSYNC_IRQ_STATUS() ( HW_PINCTRL_IRQSTAT1_CLR(GPIO_VSYNC_IRQ_BIT) )   
 157.    
 158. //! Timeout value for the VSYNC signal   
 159. #define VSYNC_TIMEOUT_TICKS TX_WAIT_FOREVER   
 160.    
 161. //! Entry mode register of the HX8347   
 162. typedef union _EntryMode    
 163. {   
 164.     uint16_t V;   
 165.     struct {   
 166.         //uint8_t LG:3;   
 167.         //uint8_t AM:1;   
 168.         //uint8_t ID:2;   
 169.         //uint8_t TY:2;   
 170.         //uint8_t DMode:2;   
 171.         //uint8_t WMode:1;   
 172.         //uint8_t OEDef:1;   
 173.         //uint8_t TRANS:1;   
 174.         //uint8_t DFM:2;   
 175.         //uint8_t VSMode:1;   
 176.          uint8_t Reserved:3;   
 177.      uint8_t BGR:1;   
 178.      uint8_t ML:1;   
 179.      uint8_t MV:1;   
 180.      uint8_t MX:1;   
 181.      uint8_t MY:1;   
 182.      uint8_t Reserved1:8;   
 183.     } B;   
 184. } Hx8347aEntryMode;//SSD1289EntryMode;   
 185.    
 186.    
 187.    
 188. //! Display control register of the SSD1289   
 189. typedef union _Hx8347aDisplayControl   
 190. {   
 191.     uint16_t V;   
 192.     struct {   
 193.         //uint8_t D0:1;   
 194.         //uint8_t D1:1;   
 195.         //uint8_t Reserved:1;   
 196.         //uint8_t CM:1;   
 197.         //uint8_t DTE:1;   
 198.         //uint8_t GON:1;   
 199.         //uint8_t Reserved2:2;   
 200.         //uint8_t SPT:1;   
 201.         //uint8_t VLE:2;   
 202.         //uint8_t PT:2;   
 203.         //uint8_t Reserved3:3;   
 204.          uint8_t Reserved:2;   
 205.      uint8_t D0:1;   
 206.      uint8_t D1:1;   
 207.      uint8_t DTE:1;   
 208.      uint8_t GON:1;   
 209.      uint8_t PT0:1;   
 210.      uint8_t PT1:1;   
 211.      uint8_t Reserved1:8;   
 212.     } B;   
 213. } Hx8347aDisplayControl;//SSD1289DisplayControl;   
 214.    
 215. ////////////////////////////////////////////////////////////////////////////////   
 216. // Prototypes   
 217. ////////////////////////////////////////////////////////////////////////////////   
 218.    
 219. #ifdef RTOS_THREADX     // VSYNC only supported in threadx builds   
 220. //! Handler for the VSYNC interrupt   
 221. //static void ddi_display_controller_VsyncIsr(void *);   
 222. #endif   
 223.    
 224. ////////////////////////////////////////////////////////////////////////////////   
 225. // Variables   
 226. ////////////////////////////////////////////////////////////////////////////////   
 227.    
 228. ////////////////////////////////////////////////////////////////////////////////   
 229. // Globals   
 230. ////////////////////////////////////////////////////////////////////////////////   
 231.    
 232. //! Current screen width in pixels, modified when display is rotated   
 233. uint16_t g_ddi_display_u16ScreenWidth = DDI_DISPLAY_DEFAULT_SIZE_HORIZONTAL;   
 234.    
 235. //! Current screen height in pixels, modified when display is rotated   
 236. uint16_t g_ddi_display_u16ScreenHeight = DDI_DISPLAY_DEFAULT_SIZE_VERTICAL;   
 237.    
 238. //! Number of DMA descriptors that the display driver has allocated.  This is   
 239. //! calculated with the NUM_DMA_DESCRIPTORS macro.  Even though this will not   
 240. //! change during run-time, it is stored as a variable to allow each controller   
 241. //! support module to define its own value and build as a lib.   
 242. uint8_t g_ddi_display_NumDmaDesc = NUM_DMA_DESCRIPTORS;   
 243.    
 244. //! Array of DMA descriptors.  These descriptors will be chained together as   
 245. //! necessary for the amount of data required to transfer for each draw operation   
 246. hw_lcdif_DmaDesc_t g_ddi_display_DmaDescChain[NUM_DMA_DESCRIPTORS] __OCRAM_NCNB_DATA;   
 247.    
 248. //! Pointer to the DMA descriptor chain.  Necessary to allow building as a lib   
 249. hw_lcdif_DmaDesc_t *g_ddi_display_pDmaDescChain = g_ddi_display_DmaDescChain;   
 250.    
 251. //! Current video mode of the driver.   
 252. ddi_display_VideoMode_t g_ddi_display_VideoMode = DDI_DISPLAY_ASYNC_MODE;   
 253.    
 254. #ifdef RTOS_THREADX     // VSYNC only supported in threadx builds   
 255. //! Semaphore for video mode operation   
 256. //static TX_SEMAPHORE *pVideoSemaphore = NULL;   
 257. #endif   
 258. ////////////////////////////////////////////////////////////////////////////////   
 259. // Code   
 260. ////////////////////////////////////////////////////////////////////////////////   
 261.    
 262. ////////////////////////////////////////////////////////////////////////////////   
 263. //! \brief static delay function   
 264. //!   
 265. //! \fntype Function   
 266. //!   
 267. //! delay function   
 268. //!    
 269. //!   
 270. ////////////////////////////////////////////////////////////////////////////////   
 271. /*  
 272. static void delay(uint32_t u32DelayValue)  
 273. {  
 274. #if defined(DDI_DISPLAY_ALL_TX_DRIVERS) && defined(RTOS_THREADX)  
 275.     tx_thread_sleep(OS_MSECS_TO_TICKS(u32DelayValue));  
 276. #else  
 277.     volatile uint32_t i;  
 278.     //u32DelayValue = u32DelayValue*1000; //// *256;  
 279.     for( i = 0; i < u32DelayValue; i++ )  
 280.     {  
 281. #pragma asm  
 282.        nop  
 283.        nop ; tmptmp  
 284.        nop ; tmptmp  
 285.        nop ; tmptmp  
 286.        nop ; tmptmp  
 287.        nop ; tmptmp  
 288.        nop ; tmptmp  
 289.        nop ; tmptmp  
 290.        nop ; tmptmp  
 291.        nop ; tmptmp  
 292. #pragma endasm          
 293.     }  
 294. #endif  
 295. }  
 296. */