<?xml version="1.0" encoding="UTF-8"?>
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<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">CLKOUT2_IBUF</arg> has no load.
</msg>

<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">LED_OUT[7]</arg> connected to top level port <arg fmt="%s" index="2">LED_OUT(7)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">LED_OUT[6]</arg> connected to top level port <arg fmt="%s" index="2">LED_OUT(6)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">LED_OUT[5]</arg> connected to top level port <arg fmt="%s" index="2">LED_OUT(5)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">LED_OUT[4]</arg> connected to top level port <arg fmt="%s" index="2">LED_OUT(4)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">LED_OUT[3]</arg> connected to top level port <arg fmt="%s" index="2">LED_OUT(3)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">LED_OUT[2]</arg> connected to top level port <arg fmt="%s" index="2">LED_OUT(2)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">LED_OUT[1]</arg> connected to top level port <arg fmt="%s" index="2">LED_OUT(1)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">LED_OUT[0]</arg> connected to top level port <arg fmt="%s" index="2">LED_OUT(0)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">EXT_INT[3]</arg> connected to top level port <arg fmt="%s" index="2">EXT_INT(3)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">EXT_INT[2]</arg> connected to top level port <arg fmt="%s" index="2">EXT_INT(2)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">EXT_INT[1]</arg> connected to top level port <arg fmt="%s" index="2">EXT_INT(1)</arg> has been removed.
</msg>

<msg type="warning" file="MapLib" num="701" delta="unknown" >Signal <arg fmt="%s" index="1">EXT_INT[0]</arg> connected to top level port <arg fmt="%s" index="2">EXT_INT(0)</arg> has been removed.
</msg>

<msg type="warning" file="LIT" num="113" delta="unknown" >Dedicated Clock IO <arg fmt="%s" index="1">IBUFG symbol &quot;CLKOUT2_IBUF&quot; (output signal=CLKOUT2_IBUF)</arg> is not driving a global clock buffer of a DLL. This configuration will result in high clock skew and long net delay.
</msg>

<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_MEMORY_15_2_4_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">MEMORY_15_3</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_12_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_13_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_21_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_14_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_22_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_15_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_23_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_16_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_24_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_17_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_25_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_18_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_26_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_19_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372" delta="unknown" >Gated clock. Clock net <arg fmt="%s" index="1">un1_TEA_20_0_a2</arg> is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="367" delta="unknown" >The signal &lt;<arg fmt="%s" index="1">CLKOUT2_IBUF</arg>&gt; is incomplete. The signal does not drive any load pins in the design.
</msg>

</messages>