library verilog;use verilog.vl_types.all;entity EMIF_COM is    port(        ARE             : in     vl_logic;        AOE             : in     vl_logic;        AWE             : in     vl_logic;        CE2             : in     vl_logic;        EXT_INT         : out    vl_logic_vector(3 downto 0);        CLKOUT2         : in     vl_logic;        TEA             : in     vl_logic_vector(3 downto 0);        TED             : inout  vl_logic_vector(15 downto 0);        LED_OUT         : out    vl_logic_vector(7 downto 0);        RST             : in     vl_logic    );end EMIF_COM;