// top.v
module top(clk_48m,RXD,key,rst,TXD);
input       clk_48m;   //系統時鐘
input       RXD;       //串口接收端
input       key;       //讀寫切換按鍵

output      rst;       //讀寫指示信號
output      TXD;       //串口發送端

wire [10:0] Waddress_temp,Raddress_temp;
wire [7:0]  datawr,datard;
wire        RI_temp,TI_temp;
wire        sendwr_temp;
wire        rst_temp;
wire [10:0] RWaddress;

assign rst = rst_temp;
assign RWaddress = rst_temp? Raddress_temp:Waddress_temp; //讀寫地址選擇

rec rec(               //接收模塊
        .clk(clk_48m),
        .RXD(RXD),
        .Dataout(datawr),
        .RI(RI_temp)
        );

send send(            //發送模塊
          .clk(clk_48m),
          .TXD(TXD),
          .TI(TI_temp),
          .WR(sendwr_temp),
          .Datain(datard)
          );

writeram u1(          //讀寫RAM控制模塊
            .key(key),
            .RI(RI_temp),
            .clk(clk_48m),
            .rst(rst_temp),
            .Waddress(Waddress_temp),
            .Raddress(Raddress_temp),
            .TI(TI_temp),
            .sendwr(sendwr_temp)
            );


 RAM2k8 u3(           //2048*8 RAM
            .DINA(datawr),
            .DOUTA(datard),
            .ADDRA(RWaddress),
            .CLKA(clk_48m),
            .BLKA(1'b0),
            .RWA(rst_temp)           
           );
endmodule