/* sngks32cSio.h - header file for Samsung KS32C serial driver *//* Copyright 2004-2005 Amine@263.net *//* Copyright 1984-2001 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01o,27jul04,a_m  BSP定制 for 思創(chuàng)S3C44B0X黃金開發(fā)板01c,16jul02,m_h  C++ protection01b,26apr01,m_h  convert tabs to spaces for readability01a,12apr01,m_h  created from snds100 template.*/#ifndef __INCsngks32cSioh#define __INCsngks32cSioh#ifdef __cplusplusextern "C" {#endif#include "sioLib.h"#include "s3c44b0x.h"/* Register offsets from Base Address*/#define SNGKS32C_ULCON         0x0000        /*UART Line Control Registers*/#define SNGKS32C_UCON          0x0004        /*UART Control Register *//* Amine: added */#define S3C44B0X_UFCON		   0x0008		 /*UART channel FIFO control register*/#define S3C44B0X_UMCON		   0x000C		 /*UART channel Modem control register*//* Amine: 0x0008->0x0010 */#define SNGKS32C_USTAT         0x0010        /*UART Status Register *//* Amine: added */#define S3C44B0X_UERSTAT       0x0014        /*UART Rx error Status Register */#define S3C44B0X_UFSTAT        0x0018        /*UART FIFO Status Register */#define S3C44B0X_UMSTAT        0x001C        /*UART Modem Status Register *//* Amine: 0x000c->0x0020 */#define SNGKS32C_UTXBUF        0x0020        /*UART Transmit Buffer Register*//* Amine: 0x0010->0x0024 */#define SNGKS32C_URXBUF        0x0024        /*UART Receive Buffer Register*//* Amine: 0x0014->0x0028 */#define SNGKS32C_UBRDIV        0x0028        /*UART Baud Rate Divisor Register*//* Amine: deleted *//*#define SNGKS32C_BRDCNT        0x0018*/     /*UART Baud Rate Count Register *//*#define SNGKS32C_BRDCLK        0x001c*/     /*UART Baud Rate Clock Monitor*//* Bit definitions within ULCON0/1 Line Control Register*/#define PARITY_NONE     0x00            /* Set No Parity*/#define PARITY_ODD      0x20            /* Set Odd Parity*/#define PARITY_EVEN     0x28            /* Set Even Parity*/#define ONE_STOP        0x00            /* One Stop Bit*/#define WORD_LEN        0x03            /* Set Word Length 8*//* Amine: deleted *//*#define INT_CLK         0x00*/         /* Internal Clock Mode *//*#define    EXT_CLK      0x40*/         /* External Clock Mode *//* Bit definitions within UCON0/1 Control Register*/#define UCON_RX          0x01            /* Receive Mode -Interrupt*//* Amine: deleted *//*#define UCON_STAT_EN     0x04*/            /* Status Interrrupt -Enable*//* Amine: 0x08->0x04 */#define UCON_TX          0x04            /* Transmit Mode-Interrupt*//* Amine: 0x01->0x00 */#define UCON_TX_DIS      0x00            /* Transmit Interrupt -Disable*//* Amine: deleted *//*#define UCON_DSR         0x20*/            /* Data Set Ready -Enable*//* Amine: 0x40->0x10 */#define UCON_BREAK       0x10            /* Set Break*//* Amine: 0xe4->0xff0 */#define UCON_RX_TX_RESET 0xff0            /* Rx and Tx Reset *//* Amine: added */#define UCON_TX_LEVEL	 0x200	#define UCON_RX_PULSE	 0x000	/* Bit definitions within USTAT0/1 Status Register*//* Amine: deleted *//*#define USTAT_DTR_LOW   0x10*/            /* DTR Enable *//*#define USTAT_DTR_HIGH  0x00*/            /* DTR Disable*//* Amine: 0x40->0x02 */#define USTAT_TX_READY  0x02            /* Transmitter Ready for another char *//* Amine: 0x20->0x01 */#define USTAT_RX_AVAIL  0x01            /* Character has arrived*/ /* Amine: deleted *//*#define USTAT_OVER_ERR  0x01*/            /* Over Run Error*//*#define USTAT_PAR_ERR   0x02*/            /* Parity Error*//*#define USTAT_FRAME_ERR 0x04*/            /* Frame Error*/ /* Amine: 0x20->0x01 */#define USTAT_RX_READY  0x01            /* Receive Data Buffer*//* Amine: added */#define UFSTAT_TX_FULL  0x200            #define UFSTAT_RX_COUNT  0x00F            /* UART Baud Rate Divisor Time Constant Value (MCLK2 = 25MHz) */#if 0	/* Amine: deleted */#define SNGKS32C_CNT0_1200   (1301<<4)    /* Baud_Rate 1200*/#define SNGKS32C_CNT0_2400    (650<<4)    /* Baud_Rate 2400*/#define SNGKS32C_CNT0_4800    (324<<4)    /* Baud_Rate 4800*/#define SNGKS32C_CNT0_9600    (162<<4)    /* Baud_Rate 9600*/#define SNGKS32C_CNT0_19200    (80<<4)    /* Baud_Rate 19200*/#define SNGKS32C_CNT0_38400    (40<<4)    /* Baud_Rate 38400*/#define SNGKS32C_CNT0_57600    (26<<4)    /* Baud_Rate 57600*/#define SNGKS32C_CNT0_115200   (13<<4)    /* Baud_Rate 115200*/#define SNGKS32C_CNT0_230400    (6<<4)    /* Baud_Rate 230400*/#define SNGKS32C_CNT0_460800    (2<<4)    /* Baud_Rate 460800*/#endif/* Amine: added *//*UBRDIVn = ((int)(fMCLK/16./baud + 0.5) -1)  波特率與系統(tǒng)主時(shí)鐘計(jì)算公式*/#define SNGKS32C_CNT0_300      (13749)    /* Baud_Rate 300*/#define SNGKS32C_CNT0_600       (6874)    /* Baud_Rate 600*/#define SNGKS32C_CNT0_1200      (3437)    /* Baud_Rate 1200*/#define SNGKS32C_CNT0_2400      (1718)    /* Baud_Rate 2400*/#define SNGKS32C_CNT0_4800       (858)    /* Baud_Rate 4800*/#define SNGKS32C_CNT0_9600       (429)    /* Baud_Rate 9600*/#define SNGKS32C_CNT0_19200      (214)    /* Baud_Rate 19200*/#define SNGKS32C_CNT0_38400      (106)    /* Baud_Rate 38400*/#define SNGKS32C_CNT0_57600       (71)    /* Baud_Rate 57600*/#define SNGKS32C_CNT0_115200      (35)    /* Baud_Rate 115200*/#define SNGKS32C_CNT0_230400      (17)    /* Baud_Rate 230400*/#define SNGKS32C_CNT0_460800       (8)    /* Baud_Rate 460800*/#define SNGKS32C_CNT1_VAL         0x00    /* Baud Rate Divisor Value*//* device and channel structures */typedef struct    {    /* must be first */    SIO_CHAN        sio;        /* standard SIO_CHAN element */    /* callbacks */    STATUS            (*getTxChar) ();    STATUS            (*putRcvChar) ();    void *            getTxArg;    void *            putRcvArg;    /* register addresses */    UINT32 *          regs;        /*UART Registers*/    /*  interrupts */    UINT8             intLevelRx;     /* recv interrupt Level for this device*/    UINT8             intLevelTx;     /* transmit interrupt Level for this device*/      /* misc */    UINT32            regDelta;       /* register address spacing */    uint_t            options;        /* Hardware options */    int               mode;           /* current mode (interrupt or poll) */    int               baudRate;       /* input clock frequency */    } SNGKS32C_CHAN;/* function prototypes */#if defined(__STDC__)extern void    sngks32cDevInit  (SNGKS32C_CHAN *pChan); extern void    sngks32cDevInit2 (SNGKS32C_CHAN *pChan); extern void    sngks32cIntRcv   (SNGKS32C_CHAN *pChan);extern void    sngks32cIntTx    (SNGKS32C_CHAN *pChan);#else   /* __STDC__ */extern void    sngks32cDevInit  ();extern void    sngks32cDevInit2 ();extern void    sngks32cIntRcv   ();extern void    sngks32cIntTx    ();#endif  /* __STDC__ */#ifdef __cplusplus}#endif#endif  /* __INCsngks32cSioh */