/* sbcarm7.h - WindRiver SBC ARM7 header file *//* Copyright 2004-2005 Amine@263.net *//* Copyright 1984-2001 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01o,28jul04,a_m  BSP定制 for 思創(chuàng)S3C44B0X黃金開發(fā)板01f,16jul02,m_h  C++ protection01e,04jan02,m_h  minor cleanup01d,03dec01,m_h  remove Diab warnings01c,27sep01,m_h  base MAC address on user DIP setting01b,22may01,m_h  documentation01a,12apr01,m_h  created from snds100 template.*//*This file contains I/O address and related constants for the SBC ARM7 board.*/#ifndef    INCsbcarm7h#define    INCsbcarm7h#ifdef __cplusplusextern "C" {#endif#include "s3c44b0x.h"#define S3C_EXC_BASE         0x0c000100	/* Amine: added */#define TARGET_SBCARM7#define SBCARM7_FLASH_BASE 0x1000000/* * Local-to-Bus memory address constants: * the local memory address always appears at 0 locally; * it is not dual ported. *//* Amine: 0x00000000->0x0c000000 */#define LOCAL_MEM_LOCAL_ADRS  0x0c000000    /* fixed */#define LOCAL_MEM_BUS_ADRS    0x00000000    /* fixed */#define BUS                   BUS_TYPE_NONE/* Amine: 50000000->66000000 */#define SBCARM7_CPU_SPEED         66000000    /* CPU clocked at 50 MHz. The timer */                    /* speed is related to this *//* definitions for the KS32C50100 UART */#define N_SBCARM7_UART_CHANNELS     2        /* number of SBCARM7 UART chans */#define N_SIO_CHANNELS          N_SBCARM7_UART_CHANNELS#define N_UART_CHANNELS         N_SBCARM7_UART_CHANNELS#define UART_REG_ADDR_INTERVAL  1        /* registers 4 bytes apart *//* LED Registers (write) */#define  SBCARM7_LEDREG             0x3fd4000/* USER DIP switch (read) */#define  SBCARM7_USERREG            0x3fd4000#define READ_USERDIP()              (*((volatile char *)SBCARM7_USERREG) & 0xff)/************************************************************************* * * DRAM Memory Bank 0 area MAP for Exception vector table  * and Stack, User code area.  * *//* Amine: 0x00000000->0x0c000000 */#define DRAM_BASE           0x0c000000   /* Final start address of DRAM */#define DRAM_LIMIT          0x400000/* Amine: 0x1000000->0x0c000000 */#define RESET_DRAM_START    0x0c000000   /* Start of DRAM on power-up */#define RESET_ROM_START     0x0          /* Start of ROM on power-up *//**************************************************************************** * * Format of the Program Status Register  */#define FBit         0x40#define IBit         0x80#define LOCKOUT      0xC0     /* Interrupt lockout value */#define LOCK_MSK     0xC0     /* Interrupt lockout mask value */#define MODE_MASK    0x1F     /* Processor Mode Mask */#define UDF_MODE     0x1B     /* Undefine Mode(UDF) */#define ABT_MODE     0x17     /* Abort Mode(ABT) */#define SUP_MODE     0x13     /* Supervisor Mode (SVC) */#define IRQ_MODE     0x12     /* Interrupt Mode (IRQ) */#define FIQ_MODE     0x11     /* Fast Interrupt Mode (FIQ) */#define USR_MODE     0x10     /* User Mode(USR) *//************************************************************************* * SYSTEM CLOCK  */#define MHz            1000000/* Amine: 50->66 */#define fMCLK_MHz      66000000     /* 50MHz, KS32C50100*/#define fMCLK          66           /* fMCLK_MHz/MHz *//************************************************************************* * SYSTEM MEMORY CONTROL REGISTER EQU TABLES  *//* SYSCFG Register Value *//* Amine: deleted *//*#define SYSCONFIG_VAL           0x07ffffa0*/    /* System Configuration Value, EDO RAM *//* Amine: 0x87ffffa0->0x00000000 */#define SYSCONFIG_VAL_SDRAM     0x00000000    /* System Configuration Value, SDRAM *//* CLKCON Clock configuration register Values */#define tCDIV           (0<<0)#define tWE             (0<<16)#define tMUX            (0<<17)#define tAC             (0<<18)#define tTEST           (0<<31)/*#define rCLKCON    (tCDIV+tWE+tMUX+tAC+tTEST)*//* Amine: deleted and added */#define rCLKCON			0x7ff8	    /*All unit block CLK enable*//* EXTACONx External I/O access timing register Values */#define tCOS0           (1<<0)#define tACS0           (1<<3)#define tCOH0           (1<<6)#define tACC0           (1<<9)#define tCOS1           (1<<16)#define tACS1           (1<<19)#define tCOH1           (1<<22)#define tACC1           (1<<25)#define rEXTACON0    (tCOS0+tACS0+tCOH0+tACC0+tCOS1+tACS1+tCOH1+tACC1)#define tCOS2           (7<<0)#define tACS2           (7<<3)#define tCOH2           (7<<6)#define tACC2           (7<<9)#define tCOS3           (7<<16)#define tACS3           (7<<19)#define tCOH3           (7<<22)#define tACC3           (7<<25)#define rEXTACON1    (tCOS2+tACS2+tCOH2+tACC2+tCOS3+tACS3+tCOH3+tACC3)/*********************************************************** * * -> EXTDBWTH : Memory Bus Width register */#define DSR0  (3<<0)     /* ROM0, 0 : Disable, 1 : Byte etc.*/#define DSR1  (1<<2)     /* ROM1  */#define DSR2  (1<<4)     /* ROM2  */#define DSR3  (0<<6)     /* ROM3  */#define DSR4  (0<<8)     /* ROM4  */#define DSR5  (0<<10)    /* ROM5  */#define DSD0  (3<<12)    /* DRAM0 */#define DSD1  (0<<14)    /* DRAM1 */#define DSD2  (0<<16)    /* DRAM2 */#define DSD3  (0<<18)    /* DRAM3 */#define DSX0  (0<<20)    /* EXTIO0*/#define DSX1  (1<<22)    /* EXTIO1*/#define DSX2  (1<<24)    /* EXTIO2*/#define DSX3  (1<<26)    /* EXTIO3*//*#define rEXTDBWTH     (DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3)*//* Amine: deleted and added */#define rEXTDBWTH  		0x11111110/* Amine: added++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ *//*FLASH0*/#define B0_Tacs         0x0     /*0clk*/#define B0_Tcos         0x0     /*0clk*/#define B0_Tacc         0x6     /*10clk*/#define B0_Tcoh         0x0     /*0clk*/#define B0_Tah          0x0     /*0clk*/#define B0_Tacp         0x0     /*0clk*/#define B0_PMC          0x0     /*normal(1data)*/#define rROMCON0 ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))/*FLASH1*/#define rROMCON1		rROMCON0/*CPLD1 External (CF Card)*/#define B2_Tacs         0x3     /*4clk*/#define B2_Tcos         0x3     /*4clk*/#define B2_Tacc         0x7     /*14clk*/#define B2_Tcoh         0x3     /*4clk*/#define B2_Tah          0x3     /*4clk*/#define B2_Tacp         0x3     /*6clk*/#define B2_PMC          0x0     /*normal(1data)*/#define rROMCON2 ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))/*CPLD2 Exernal (Net)*/#define rROMCON3		rROMCON2/*CPLD3 USER FREE*/#define rROMCON4		rROMCON2/*CPLD4 Internal*/#define rROMCON5		rROMCON2/*SDRAM1 Bank 6 parameter*//*BDRAMTYPE="DRAM"       ;MT=01(FP DRAM) or 10(EDO DRAM)*/ #define B6_MT           0x3     /*SDRAM*/#define B6_Trcd         0x0     /*2clk*/#define B6_SCAN         0x0     /*8bit*/#define rSDRAMCON0 ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))/*SDRAM2 Bank 7 parameter*/#define rSDRAMCON1		rSDRAMCON0/*REFRESH parameter*/#define REFEN           0x1     /*Refresh enable*/#define TREFMD          0x0     /*CBR(CAS before RAS)/Auto refresh*/#define Trp             0x1     /*3clk*/#define Trc             0x1     /*5clk*/#define Tchr            0x2     /*3clk*//*REFCNT = 2048 + 1 - MCLK(MHz) * 15.6*/#define REFCNT          1020    /*period=15.6us, MCLK=66Mhz*/#define rSREFEXTCON ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)#define rBANKSIZE		0x10	/*SCLK power down mode, BANKSIZE 32M/32M*/#define rMRSRB6			0x20	/*MRSR6 CL=2clk*/#define rMRSRB7			0x20	/*MRSR7*//*PLLCLK = 66000000     ;Freq calc：    ;Fout = (8+ M_DIV)*Fout/[(2+P_DIV)*2]*/    #define M_DIV   		58      /*Fout = Fin * 2*/#if(BOARD_TYPE == BOARD_ARM3000)#define P_DIV   		1#else#define P_DIV   		3#endif#define S_DIV   		1#define rPLLCON ((M_DIV<<12)+(P_DIV<<4)+S_DIV)	/*Fin=10MHz,Fout=40MHz*/#define rLOCKTIME		0xfff/* Amine: added++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */#if 0 /* Amine: deleted *//*********************************************************** * * -> ROMCON0 : ROM Bank0 Control register  */#define ROMBasePtr0     (0x0<<10)                      /*=0x00000000*/#define ROMBasePtr0_S   (0x100<<10)                    /*=0x01000000*/#define ROMEndPtr0      ((ROM_SIZE>>12)<<20)           /*=0x00200000*/#define ROMEndPtr0_S    (((ROM_SIZE>>12)+0x100)<<20)   /*=0x01200000*/#define PMC0            0x0             /* 0x0=Normal ROM, 0x1=4Word Page etc.*/#define rTpa0           (0x0<<2)        /* 0x0=5Cycle, 0x1=2Cycle etc.*/#define rTacc0          (0x6<<4)        /* 0x0=Disable, 0x1=2Cycle etc.*/#define rROMCON0        (ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0)#define rROMCON0_S      (ROMEndPtr0_S+ROMBasePtr0_S+rTacc0+rTpa0+PMC0)/*************************************************************************** * -> ROMCON1 : ROM Bank1 Control register, Mailbox Interface */