#define ROMBasePtr1     (0x3fc<<10)                 /*=0x0fc0000*/#define ROMEndPtr1      ((0xfd0000>>12)<<20)        /*=0x0fd0000*/#define PMC1            0x0             /* 0x0=Normal ROM, 0x1=4Word Page etc.*/#define rTpa1           (0x0<<2)        /* 0x0=5Cycle, 0x1=2Cycle etc.*/#define rTacc1          (0x6<<4)        /* 0x0=Disable, 0x1=2Cycle etc.*/#define rROMCON1        (ROMEndPtr1+ROMBasePtr1+rTacc1+rTpa1+PMC1)/*************************************************************************** * -> ROMCON2 : ROM Bank2 Control register, EEPROM */#define ROMBasePtr2     (0x3fb<<10)                 /*=0x0fb0000*/#define ROMEndPtr2      ((0xfc0000>>12)<<20)       /*=0x0fc0000*/#define PMC2            0x0             /* 0x0=Normal ROM, 0x1=4Word Page etc.*/#define rTpa2           (0x0<<2)        /* 0x0=5Cycle, 0x1=2Cycle etc.*/#define rTacc2          (0x6<<4)        /* 0x0=Disable, 0x1=2Cycle etc.*/#define rROMCON2        (ROMEndPtr2+ROMBasePtr2+rTacc2+rTpa2+PMC2)/*************************************************************************** * -> ROMCONx : unused ROM Bank Control registers */#define rROMCON3      0x60#define rROMCON4      0x60#define rROMCON5      0x60        /*ROMEndPtr5+ROMBasePtr5+rTacc5+rTpa5+PMC5*//**************************************************************************** * -> DRAMCON0 : RAM Bank0 control register  (EDO) */#define EDO_Mode0          1             /*(EDO)0=Normal, 1=EDO DRAM*/#define CasPrechargeTime0  1             /*(Tcp)0=1cycle,1=2cycle*/#define CasStrobeTime0     1             /*(Tcs)0=1cycle ~ 3=4cycle*/#define DRAMCON0Reserved   1             /* Must be set to 1*/#define RAS2CASDelay0      0             /*(Trc)0=1cycle,1=2cycle*/#define RASPrechargeTime0  1             /*(Trp)0=1cycle ~ 3=4clcyle*/#define DRAMBasePtr0       (0x100<<10)   /*=0x1000000 */#define DRAMBasePtr0_S     0x00          /* now RAM moved to zero */#define DRAMEndPtr0        (((LOCAL_MEM_SIZE >> 16) + 0x100) << 20)  /*=0x00800000 - 8 MB */#define DRAMEndPtr0_S      ((LOCAL_MEM_SIZE >> 16) << 20)  /*=0x00800000 - 8 MB */#define NoColumnAddr0      2             /*0=8bit,1=9bit,2=10bit,3=11bits*/#define Tcs0           (CasStrobeTime0<<1)#define Tcp0           (CasPrechargeTime0<<3)#define dumy0          (DRAMCON0Reserved<<4)        /*dummy cycle*/#define Trc0           (RAS2CASDelay0<<7)#define Trp0           (RASPrechargeTime0<<8)#define CAN0           (NoColumnAddr0<<30)#define rDRAMCON0      (CAN0+DRAMEndPtr0+DRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)#define rDRAMCON0_S    (CAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)/**************************************************************************** * -> DRAMCONx : unused RAM Banks */#define rDRAMCON1         0x00#define rDRAMCON2         0x00#define rDRAMCON3         0x00/**************************************************************************** * -> DRAMCON0 : RAM Bank0 control register (for SDRAM) */#define SRAS2CASDelay0          1                    /*(Trc)0=1cycle,1=2cycle*/#define SRASPrechargeTime0      3                    /*(Trp)0=1cycle ~ 3=4cycle*/#define SCasPrechargeTime0      0                    /*(Tcp)0=1cycle,1=2cycle*/#define SCasStrobeTime0         0                    /*(Tcs)0=1cycle ~ 3=4cycle*/#define SNoColumnAddr0          0                    /*0=8bit,1=9bit,2=10bit,3=11bits*/#define SCAN0                   (SNoColumnAddr0<<30)#define STrc0                   (SRAS2CASDelay0<<7)#define STrp0                   (SRASPrechargeTime0<<8)#define STcp0                   (SCasPrechargeTime0<<3)#define STcs0                   (SCasStrobeTime0<<1)#define rSDRAMCON0              (SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0+STcp0+STcs0)#define rSDRAMCON0_S            (SCAN0+DRAMEndPtr0_S+DRAMBasePtr0_S+STrp0+STrc0+STcp0+STcs0)/**************************************************************************** * -> DRAMCONx : unused SYNC DRAM Banks */#define rSDRAMCON1        0x00#define rSDRAMCON2        0x00#define rSDRAMCON3        0x00/************************************************************************** * -> REFEXTCON : External I/O & Memory Refresh cycle Control Register  */#define RefCycle          16         /*Unit [us], 1k refresh 16ms*//*RefCycle EQU 8 ;Unit [us], 1k refresh 16ms*/#define CASSetupTime         0         /*0=1cycle, 1=2cycle*/#define CASHoldTime          0         /*0=1cycle, 1=2cycle, 2=3cycle,                                         3=4cycle, 4=5cycle,*/#if (((2<<11)+1-(RefCycle*fMCLK)) < 0x3FF)#define RefCycleValue     (((2<<11)+1-(RefCycle*fMCLK))<<21)#else#define RefCycleValue     (0x3FF<<21)#endif#define Tcsr              (CASSetupTime<<20) /* 1cycle */#define Tcs               (CASHoldTime<<17)#define ExtIOBase         0x183fd            /* Refresh enable, VSF=1*/#define rREFEXTCON        (RefCycleValue+Tcsr+Tcs+ExtIOBase)/****************************************************************** *SRefCycle EQU 16 ;Unit [us], 4k refresh 64ms */#define SRefCycle          8         /*Unit [us], 4k refresh 64ms*/#define ROWcycleTime       3         /*0=1cycle, 1=2cycle, 2=3cycle,                                       3=4cycle, 4=5cycle,*/#define SRefCycleValue     ((2048+1-(SRefCycle*fMCLK))<<21)#define STrc               (ROWcycleTime<<17)#define rSREFEXTCON        (SRefCycleValue+STrc+ExtIOBase)#endif /*#if 0*//* interrupt levels */ /* Amine: 注意編號順序,和4510相反,修改較多 */#define INT_LVL_EXTINT0       25    /* External Interrupt0 */#define INT_LVL_EXTINT1       24    /* External Interrupt1 */#define INT_LVL_EXTINT2       23    /* External Interrupt2 */#define INT_LVL_EXTINT3       22    /* External Interrupt3 */#define INT_LVL_EXTINTn       21    /* External Interrupt4/5/6/7 */#define INT_LVL_TICK          20    #define INT_LVL_ZDMA0         19    #define INT_LVL_ZDMA1         18    #define INT_LVL_BDMA0         17    #define INT_LVL_BDMA1         16    #define INT_LVL_WDT           15  #define INT_LVL_UERR01        14 #define INT_LVL_TIMER0        13    /* Timer 0 Interrupt */#define INT_LVL_TIMER1        12    /* Timer 1 Interrupt  */#define INT_LVL_TIMER2        11#define INT_LVL_TIMER3        10#define INT_LVL_TIMER4         9#define INT_LVL_TIMER5         8#define INT_LVL_UARTRX0        7    /* UART 0 Receive & Error Interrupt */#define INT_LVL_UARTRX1        6    /* UART 1 Receive & Error Interrupt */#define INT_LVL_IIC            5 #define INT_LVL_SIO            4 #define INT_LVL_UARTTX0        3    /* UART 0 Transmit Interrupt */#define INT_LVL_UARTTX1        2    /* UART 1 Transmit Interrupt */#define INT_LVL_RTC            1 #define INT_LVL_ADC            0 /* interrupt vectors */#define INT_VEC_EXTINT0     IVEC_TO_INUM(INT_LVL_EXTINT0)    /* External Interrupt0 */#define INT_VEC_EXTINT1     IVEC_TO_INUM(INT_LVL_EXTINT1)    /* External Interrupt1*/#define INT_VEC_EXTINT2     IVEC_TO_INUM(INT_LVL_EXTINT2)    /* External Interrupt2*/#define INT_VEC_EXTINT3     IVEC_TO_INUM(INT_LVL_EXTINT3)    /* External Interrupt3*/#define INT_VEC_UARTTX0     IVEC_TO_INUM(INT_LVL_UARTTX0)    /* UART 0 Transmit Interrupt */#define INT_VEC_UARTRX0     IVEC_TO_INUM(INT_LVL_UARTRX0)    /* UART 0 Receive & Error Interrupt */#define INT_VEC_UARTTX1     IVEC_TO_INUM(INT_LVL_UARTTX1)    /* UART 1 Transmit Interrupt */#define INT_VEC_UARTRX1     IVEC_TO_INUM(INT_LVL_UARTRX1)    /* UART 1 Receive & Error Interrupt */#if 0 /* Amine: deleted */#define INT_VEC_GDMA0       IVEC_TO_INUM(INT_LVL_GDMA0)    /* GDMA channel 0 interrupt*/#define INT_VEC_GDMA1       IVEC_TO_INUM(INT_LVL_GDMA1)    /* GDMA channel 0 interrupt*/#endif#define INT_VEC_TIMER0      IVEC_TO_INUM(INT_LVL_TIMER0)    /* Timer 0 Interrupt  */#define INT_VEC_TIMER1      IVEC_TO_INUM(INT_LVL_TIMER1)    /* Timer 1 Interrupt */#if 0 /* Amine: deleted */#define INT_VEC_HDLCTxA     IVEC_TO_INUM(INT_LVL_HDLCTxA)    /* HDLC channel A Tx interrupt */#define INT_VEC_HDLCRxA     IVEC_TO_INUM(INT_LVL_HDLCRxA)    /* HDLC channel A Rx interrupt*/#define INT_VEC_HDLCTxB     IVEC_TO_INUM(INT_LVL_HDLCTxB)    /* HDLC channel B Tx interrupt*/#define INT_VEC_HDLCRxB     IVEC_TO_INUM(INT_LVL_HDLCRxB)    /* HDLC channel B Rx interrupt*/#define INT_VEC_BDMATx      IVEC_TO_INUM(INT_LVL_BDMATx)    /* Ethernet controller BDMA Tx Interrupt */#define INT_VEC_BDMARx      IVEC_TO_INUM(INT_LVL_BDMARx)    /* Ethernet controller BDMA Rx Interrupt */#define INT_VEC_MACTx       IVEC_TO_INUM(INT_LVL_MACTx)    /* Ethernet controller MAC Tx Interrupt*/#define INT_VEC_MACRx       IVEC_TO_INUM(INT_LVL_MACRx)    /* Ethernet controller MAC Rx Interrupt */#endif#define INT_VEC_IIC         IVEC_TO_INUM(INT_LVL_IIC)        /* IIC -Bus Interrupt *//********************************************************************************************************** * Cache Definitions * */#define SBCARM7_CACHE_0K   	 	(0<<1)#define SBCARM7_CACHE_4K        (1<<1)#define SBCARM7_CACHE_8K        (3<<1)#define SBCARM7_WRITE_BUFF      (1<<3)#define SBCARM7_CACHE_MODE      0x0E#define SBCARM7_CACHE_SIZE		SBCARM7_CACHE_8K#define NON_CACHE_REGION    	0		/*TODO*//*#define SBCARM7_TAGRAM          0x11000000*/#define SBCARM7_TAGRAM_BEG 0x10002000  /*CACHE TAG RAM起始地址*/#define SBCARM7_TAGRAM_END 0x10004800  /*CACHE TAG RAM結(jié)束地址*//* * * definitions for the SBCARM7 Timer: * two timers clocked from same source and with the same reload overhead */#define SBCARM7_TIMER_SYS_TC_DISABLE    (TC_DISABLE | TC_PERIODIC | TC_DIV16)#define SBCARM7_TIMER_SYS_TC_ENABLE     (TC_ENABLE  | TC_PERIODIC | TC_DIV16)#define SBCARM7_TIMER_AUX_TC_DISABLE    (TC_DISABLE | TC_PERIODIC | TC_DIV16)#define SBCARM7_TIMER_AUX_TC_ENABLE     (TC_ENABLE  | TC_PERIODIC | TC_DIV16)#define SYS_TIMER_CLK               (SBCARM7_CPU_SPEED)    /* Frequency of counter/timer */#define AUX_TIMER_CLK               (SBCARM7_CPU_SPEED)    /* Frequency of counter/timer */#define SBCARM7_RELOAD_TICKS            3        /* three ticks to reload timer */#define SYS_TIMER_CLEAR(x)          (SBCARM7_TIMER_T1CLEAR(x))    /* sys Clk is timer 1  */#define SYS_TIMER_CTRL(x)           (SBCARM7_TIMER_T1CTRL(x))#define SYS_TIMER_LOAD(x)           (SBCARM7_TIMER_T1LOAD(x))#define SYS_TIMER_VALUE(x)          (SBCARM7_TIMER_T1VALUE(x))#define SBCARM7_TIMER_VALUE_MASK        0xFFFF#define AUX_TIMER_CLEAR(x)          (SBCARM7_TIMER_T2CLEAR(x))    /* aux Clk is timer 2  */#define AUX_TIMER_CTRL(x)           (SBCARM7_TIMER_T2CTRL(x))#define AUX_TIMER_LOAD(x)           (SBCARM7_TIMER_T2LOAD(x))#define AUX_TIMER_VALUE(x)          (SBCARM7_TIMER_T2VALUE(x))#if (BOARD_TYPE == BOARD_ARMEPS)#define SYS_TIMER_INT_LVL           (INT_LVL_TIMER5)#else#define SYS_TIMER_INT_LVL           (INT_LVL_TIMER0)#endif#define AUX_TIMER_INT_LVL           (INT_LVL_TIMER1)/****************************************************************************************** * Clock rates depend upon CPU power and work load of application. * The values below are minimum and maximum allowed by the hardware. * Note that it takes 3 ticks to reload the 16-bit counter and we don't * accept values that would mean a zero reload value as we don't know what * that will do. * So: * min frequency = roundup(clock_rate/(max_counter_value+3)) * max frequency = rounddown(clock_rate/(min_counter_value+3)) * i.e.              SYS_CLK_RATE_MAX (SYS_TIMER_CLK/4) * However, we must set maxima that are sustainable on a running * system. Experiments suggest that a 16MHz PID board can sustain a * maximum clock rate of 10000 to 10500. The values below have been * chosen so that there is a reasonable margin and the BSP passes the * test suite. */#define SYS_CLK_RATE_MIN      10#define SYS_CLK_RATE_MAX      10000#define AUX_CLK_RATE_MIN      2#define AUX_CLK_RATE_MAX      10000#define SBCARM7_RESET_RAM_BASE    0x1000000  RAM base in reset memory map */ /* * Our MAC address definition.  User can change this value as * per requirement.  Note, the least significant byte of the * address is changed to the value of the user DIP switch setting. * SW4-D0 is the least significant bit of this byte.  Open=0. */#define ETHERNET_MAC_ADRS { 0x00, 0xA0, 0x88, 0x88, 0x88, 0x00 }#ifdef __cplusplus}#endif#endif    /* INCsbcarm7h */