/*------------------------------------------------------------------------*
 *  FILE:  MASKS860.H                                                     *
 *          														               	  *
 *  DESCRIPTION:  Bit masks for MPC860 registers. Sequence of registers   *
 *                follows device memory map exactly. 				      	  *
 *																		                    * 
 *  REGISTERS NOT														                 *
 *  INCLUDED:  SWSR, SCCRK, PLPRCRK, RSRK, SDAR, SDMR, IDMR1, IDMR2,      *
 *				   TRR1-4, TCR1-4, TCN1-4, PSMR1, SCCE1, SCCM1, SCCS1,        *
 *             PSMR2, PSMR3, SCCE3, SCCM3, SCCS3, PSMR4, SCCE4,	        *
 *             SCCM4, SCCS4, SIRP				         			           *
 *																		                    *
 *  Note: Look in the Protocol Specific section below first before        *
 *        determining that the above registers are not covered.           *
 *										    							                    * 
 *																		                    *
 *  HISTORY:  9/30/97  ecg  Created								                 *
 *            11/17/97 jay  Modified                                      *
 *            1/9/98   ecg  Modified     								           *
 *            3/11/98  jay  changed smc2/pip to smc2_pip                  *
 *------------------------------------------------------------------------*/

/*------------------------------------------------------------------------*
 *                           GENERAL PURPOSE MASKS			    		        *
 *------------------------------------------------------------------------*/
 
#define  ALL_ONES    0xFFFFFFFF
#define  ALL_ZEROS   0x00000000


/*------------------------------------------------------------------------*
 *                              GENERAL SIU							           *
 *------------------------------------------------------------------------*/
                                                                            

/*----------------------------------------*
 * Module Configuration Register (SIUMCR) *
 *----------------------------------------*/

#define SIUMCR_EARB  0x80000000   /* External Arbitration */
#define SIUMCR_EARP  0x70000000   /* External Arbitration Req. Priority */
#define RESERVED1    0x0F000000   
#define SIUMCR_DSHW  0x00800000   /* Data Show Cycles */
#define SIUMCR_DBGC  0x00600000   /* Debug Pins Configuration */
#define SIUMCR_DBPC  0x00180000   /* Debug Port Pins Configuration */
#define RESERVED2    0x00040000       
#define SIUMCR_FRC   0x00020000   /* FRZ Pin configuration */
#define SIUMCR_DLK   0x00010000   /* Debug Register Lock */
#define SIUMCR_PNCS  0x00008000   /* Parity Enable Nonmemory Controller
                                      Regions */  
#define SIUMCR_OPAR  0x00004000   /* Odd Parity */
#define SIUMCR_DPC   0x00002000   /* Data Parity Pins Configuration */
#define SIUMCR_MPRE  0x00001000   /* Multiprocessors Reservation Enable */
#define SIUMCR_MLRC  0x00000C00   /* Multi-Level Reservation Control */
#define SIUMCR_AEME  0x00000200   /* Asynchronous External Master Enable */
#define SIUMCR_SEME  0x00000100   /* Synchronous External Master Enable */
#define SIUMCR_BSC   0x00000080   /* Byte Select Configuration */
#define SIUMCR_GB5E  0x00000040   /* GPL_B(5) Enable */
#define SIUMCR_B2DD  0x00000020   /* Bank 2 Double Drive */
#define SIUMCR_B3DD  0x00000010   /* Bank 3 Double Drive */
#define RESERVED3    0x0000000F        



/*------------------------------------------------------*
 * System Protection Control Register (SYPCR)           *
 *------------------------------------------------------*/

#define SYPCR_SWTC  0xFFFF0000     /* SoftWare Watchdog Timer Count */
#define SYPCR_BMT   0x0000FF00     /* Bus Monitor Timing */
#define SYPCR_BME   0x00000080     /* Bus Monitor Enable */
#define RESERVED4   0x00000070
#define SYPCR_SWF   0x00000008     /* Software Watchdog Freeze */
#define SYPCR_SWE   0x00000004     /* Software Watchdog Enable */
#define SYPCR_SWRI  0x00000002     /* Software Watchdog Reset/Interrupt 
                                       Select */
#define SYPCR_SWP   0x00000001     /* Software Watchdog Prescale */



/*-------------------------------------------------------------*
 * Software Service Register (SWSR)                            *
 *-------------------------------------------------------------*
 * NOTE: Bit masks are not provided for the Software Service   *
 *       Register (SWSR). The SWSR is the location to which    *
 *       the SWT servicing sequence is written. To prevent SWT *
 *       timeout, the user should write $556C followed by 	   *
 *       $AA93 to this register. The SWSR can be written at    *
 *       any time, but returns all zeros when read.            *
 *-------------------------------------------------------------*/ 



/*-------------------------------------*
 * Interrupt Pending Register (SIPEND) *
 *-------------------------------------*/

#define SIPEND_IRQ0  0x80000000
#define SIPEND_LVL0  0x40000000
#define SIPEND_IRQ1  0x20000000
#define SIPEND_LVL1  0x10000000
#define SIPEND_IRQ2  0x08000000
#define SIPEND_LVL2  0x04000000
#define SIPEND_IRQ3  0x02000000
#define SIPEND_LVL3  0x01000000
#define SIPEND_IRQ4  0x00800000
#define SIPEND_LVL4  0x00400000
#define SIPEND_IRQ5  0x00200000
#define SIPEND_LVL5  0x00100000
#define SIPEND_IRQ6  0x00080000
#define SIPEND_LVL6  0x00040000
#define SIPEND_IRQ7  0x00020000
#define SIPEND_LV7   0x00010000
#define RESERVED5    0x0000FFFF


/*-----------------------------------------*
 *   SIU Interrupt Mask Register (SIMASK)  *
 *-----------------------------------------*/

#define SIMASK_IRM0  0x80000000
#define SIMASK_LVM0  0x40000000
#define SIMASK_IRM1  0x20000000
#define SIMASK_LVM1  0x10000000
#define SIMASK_IRM2  0x08000000
#define SIMASK_LVM2  0x04000000
#define SIMASK_IRM3  0x02000000
#define SIMASK_LVM3  0x01000000
#define SIMASK_IRM4  0x00800000
#define SIMASK_LVM4  0x00400000
#define SIMASK_IRM5  0x00200000
#define SIMASK_LVM5  0x00100000
#define SIMASK_IRM6  0x00080000
#define SIMASK_LVM6  0x00040000
#define SIMASK_IRM7  0x00020000
#define SIMASK_LVM7  0x00010000
#define RESERVED6    0x0000FFFF



/*---------------*
 * SIEL Register *
 *---------------*/

#define SIEL_ED0   0x80000000      
#define SIEL_WM0   0x40000000
#define SIEL_ED1   0x20000000
#define SIEL_WM1   0x10000000
#define SIEL_ED2   0x08000000
#define SIEL_WM2   0x04000000
#define SIEL_ED3   0x02000000
#define SIEL_WM3   0x01000000
#define SIEL_ED4   0x00800000
#define SIEL_WM4   0x00400000
#define SIEL_ED5   0x00200000
#define SIEL_WM5   0x00100000
#define SIEL_ED6   0x00080000
#define SIEL_WM6   0x00040000
#define SIEL_ED7   0x00020000
#define SIEL_WM7   0x00010000
#define RESERVED7  0x0000FFFF



/*---------------------------------------*
 * SIU Interrupt Vector Register (SIVEC) *
 *---------------------------------------*/

#define SIVEC_INTCODE   0xFF000000  /* Interrupt Code */



/*---------------------------------------*
 * Transfer Error Status Register (TESR) *
 *---------------------------------------*/

#define RESERVED8  0xC000
#define TESR_IEXT  0x2000    /* Instruction External Transfer Error 
                                 Acknowledge */
#define TESR_IBM   0x1000    /* Instruction transfer Monitor Timeout */ 
#define TESR_IPB0  0x0800    /* Instruction Parity Error on Byte */
#define TESR_IPB1  0x0400    /* Instruction Parity Error on Byte */
#define TESR_IPB2  0x0200    /* Instruction Parity Error on Byte */
#define TESR_IPB3  0x0100    /* Instruction Parity Error on Byte */
#define RESERVED9  0x00C0   
#define TESR_DEXT  0x0020    /* Data External Transfer Error Acknowledge */
#define TESR_DBM   0x0010    /* Data Transfer Monitor Timeout */
#define TESR_DPB0  0x0008    /* Data Parity Error on Byte */
#define TESR_DPB1  0x0004    /* Data Parity Error on Byte */
#define TESR_DPB2  0x0002    /* Data Parity Error on Byte */
#define TESR_DPB3  0x0001    /* Data Parity Error on Byte */ 



/*------------------------------------*
 * SDMA Configuration Register (SDCR) *
 *------------------------------------*/

#define RESERVED10   0xFFFF8000    
#define SDCR_FRZ     0x00006000   /* Freeze */
#define RESERVED11   0x00001FF0
#define RESERVED12   0x000000C0
#define SDCR_RAID    0x00000003   /* RISC Controller Arbitration ID */




/*-------------------------------------------------------------------------*
 *                                  PCMCIA								   *
 *-------------------------------------------------------------------------*/
                                                                            

/*------------------------------------*
 * Interface Option Register 0 (POR0) *
 *------------------------------------*/

#define POR0_BSIZE  0xF8000000    /* PCMCIA Bank Size */
#define RESERVED13  0x07F00000	  
#define POR0_PSHT   0x000F0000    /* PCMCIA Strobe Hold Time */
#define POR0_PSST   0x0000F000    /* PCMCIA Strobe Set Up Time */
#define POR0_PSL    0x00000F80    /* PCMCIA Strobe Length */
#define POR0_PPS    0x00000040    /* PCMCIA Port Size */
#define POR0_PRS    0x00000038    /* PCMCIA Region Select */
#define POR0_PSLOT  0x00000004    /* PCMCIA Slot Identifier */
#define RESERVED14  0x00000002    /* Any write to this window will result
                                      in a bus error */
#define POR0_PV     0x00000001    /* PCMCIA Valid Bit */



/*------------------------------------*
 * Interface Option Register 1 (POR1) *
 *------------------------------------*/

#define POR1_BSIZE  0xF8000000    /* PCMCIA Bank Size */
#define RESERVED15  0x07F00000	  
#define POR1_PSHT   0x000F0000    /* PCMCIA Strobe Hold Time */
#define POR1_PSST   0x0000F000    /* PCMCIA Strobe Set Up Time */
#define POR1_PSL    0x00000F80    /* PCMCIA Strobe Length */
#define POR1_PPS    0x00000040    /* PCMCIA Port Size */
#define POR1_PRS    0x00000038    /* PCMCIA Region Select */
#define POR1_PSLOT  0x00000004    /* PCMCIA Slot Identifier */
#define RESERVED16  0x00000002    /* Any write to this window will result
                                      in a bus error */
#define POR1_PV     0x00000001    /* PCMCIA Valid Bit */



/*------------------------------------*
 * Interface Option Register 2 (POR2) *
 *------------------------------------*/

#define POR2_BSIZE  0xF8000000    /* PCMCIA Bank Size */
#define RESERVED17  0x07F00000	  
#define POR2_PSHT   0x000F0000    /* PCMCIA Strobe Hold Time */
#define POR2_PSST   0x0000F000    /* PCMCIA Strobe Set Up Time */
#define POR2_PSL    0x00000F80    /* PCMCIA Strobe Length */
#define POR2_PPS    0x00000040    /* PCMCIA Port Size */
#define POR2_PRS    0x00000038    /* PCMCIA Region Select */
#define POR2_PSLOT  0x00000004    /* PCMCIA Slot Identifier */
#define RESERVED18  0x00000002    /* Any write to this window will result
                                      in a bus error */
#define POR2_PV     0x00000001    /* PCMCIA Valid Bit */



/*------------------------------------*
 * Interface Option Register 3 (POR3) *
 *------------------------------------*/

#define POR3_BSIZE  0xF8000000    /* PCMCIA Bank Size */
#define RESERVED19  0x07F00000	  
#define POR3_PSHT   0x000F0000    /* PCMCIA Strobe Hold Time */
#define POR3_PSST   0x0000F000    /* PCMCIA Strobe Set Up Time */
#define POR3_PSL    0x00000F80    /* PCMCIA Strobe Length */
#define POR3_PPS    0x00000040    /* PCMCIA Port Size */
#define POR3_PRS    0x00000038    /* PCMCIA Region Select */
#define POR3_PSLOT  0x00000004    /* PCMCIA Slot Identifier */
#define RESERVED20  0x00000002    /* Any write to this window will result
                                      in a bus error */
#define POR3_PV     0x00000001    /* PCMCIA Valid Bit */



/*------------------------------------*
 * Interface Option Register 4 (POR4) *
 *------------------------------------*/

#define POR4_BSIZE  0xF8000000    /* PCMCIA Bank Size */
#define RESERVED21  0x07F00000	  
#define POR4_PSHT   0x000F0000    /* PCMCIA Strobe Hold Time */
#define POR4_PSST   0x0000F000    /* PCMCIA Strobe Set Up Time */
#define POR4_PSL    0x00000F80    /* PCMCIA Strobe Length */
#define POR4_PPS    0x00000040    /* PCMCIA Port Size */
#define POR4_PRS    0x00000038    /* PCMCIA Region Select */
#define POR4_PSLOT  0x00000004    /* PCMCIA Slot Identifier */
#define RESERVED22  0x00000002    /* Any write to this window will result
                                      in a bus error */
#define POR4_PV     0x00000001    /* PCMCIA Valid Bit */



/*------------------------------------*
 * Interface Option Register 5 (POR5) *
 *------------------------------------*/

#define POR5_BSIZE  0xF8000000    /* PCMCIA Bank Size */
#define RESERVED23  0x07F00000	  
#define POR5_PSHT   0x000F0000    /* PCMCIA Strobe Hold Time */
#define POR5_PSST   0x0000F000    /* PCMCIA Strobe Set Up Time */
#define POR5_PSL    0x00000F80    /* PCMCIA Strobe Length */
#define POR5_PPS    0x00000040    /* PCMCIA Port Size */