;************************************************************************************************
;Chinese Academy of Sciences, Institute of Automation
;File Name:	Init.s
;Description:	Write Flash 4 Bytes 
;Author:		YuLihua
;Date:		    2004-6-4
;************************************************************************************************
;Entry:	0x3000,0000
;       Use mymap.txt config the SFR
;FLASH:	0x0000,0000~0x0080,0000    Total: 4MB
;SDRAM: 0x3000,0000~0x3800,0000	   Total:64MB
;************************************************************************************************	

	
	IMPORT  Main
	AREA    Init,CODE,READONLY
	
	ENTRY
;	/*
;	 * set the cpu to SVC32 mode
;	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
;/*
;        bic     r0,r0,#0x80
;*/
	msr	cpsr_cf,r0
	
;	/* 
;	 * Following registers mapping got from hardware engineer,for more infomation
;	 * please contact Mafuyun
;	 */

;	/* 
;	 * watchdog timer disable 
;	 */

	ldr     r0, =0x53000000
	ldr     r1, =0x00008020
	str     r1, [r0]

;	/* 
;	 * interrupt service masked 
;	 * remarked for that it is the reset-value
;	 */

	ldr     r0, =0x4a000008
	ldr     r1, =0xffffffff
	str     r1, [r0]
	
	ldr     r0, =0x4a00001c
	ldr     r1, =0xffffffff
	str     r1, [r0]

;	/* 
;	 * LOCK TIME COUNT REGISTER
;	 * remarked for that it is the reset-value
;	 */

;	//WriteAddr 0x4c000000,0x00ffffff
;
;	/* 
;	 * MPLL configuration register
;	 * 16.384*(0x64+8)/10=176.9472M
;	 */
	
	ldr     r0, =0x4c000004
	ldr     r1, =0xa1031;f0=12MHz,Mpll=202.8MHz
	str     r1, [r0]

;	/* 
;	 * Clock divider control register
;	 * PCLK:HCLK:FCLK=1:2:4
;	 */

	ldr     r0, =0x4c000014
	ldr     r1, =0x00000003
	str     r1, [r0]
	
;	/*
;	 * Memory Control
;	 */

;	/*
;	 * BUS WIDTH & WAIT CONTROL
;	 * Bank 0,1,6,7 32-bit bus width
;	 * others using the default value
;         * cpci wait signal 0x22111124 TO 0x22111164
;         * tacc=4 
;         * Dsp bank request 0x48000000,0x####2###
;	 */	

	ldr     r0, =0x48000000
	ldr     r1, =0x22112162
	str     r1, [r0]
    
	ldr     r0, =0x48000008
	ldr     r1, =0x00000340
	str     r1, [r0]

;	/* 
;	 * Bank control 
;  	 * Bank3(for dsp hpi) using the max clocks
;	 * others using the default value(remaked)       
;	 */ 


;	//WriteAddr 0x48000004,0x00000700
;	//WriteAddr 0x48000008,0x00000700
;	//WriteAddr 0x4800000c,0x00000700
	
;	/*
;	 * Dsp hpi port
;	 */
	ldr     r0, =0x48000010
	ldr     r1, =0x00007ff0
	str     r1, [r0]
	
;	//WriteAddr 0x48000014,0x00000700
;	//WriteAddr 0x48000018,0x00000700
;	//WriteAddr 0x4800001c,0x00018009
;	//WriteAddr 0x48000020,0x00018009
	
;	/*
;        * SDRAM refresh control register
;	 * Refresh period = (211-refresh_count+1)/HCLK
;	 * refresh_count=0x0552
;         * HCLK=88.4736
;         * Refresh period=7.75us
;         */

	ldr     r0, =0x48000024
	ldr     r1, =0x00ac0552
	str     r1, [r0]

;	/* 
;         * I don't know the following function clearly
;         */

	ldr     r0, =0x48000028
	ldr     r1, =0x00000011
	str     r1, [r0]
	
	ldr     r0, =0x4800002c
	ldr     r1, =0x00000030
	str     r1, [r0]
	
	ldr     r0, =0x48000030
	ldr     r1, =0x00000030
	str     r1, [r0]
	
	ldr     sp, =0x33000000

;/*
;	ldr     r0, =0x56000044
;	ldr     r1, =0xffffffff
;	str     r1, [r0]
;*/


;        /*
;	 * Led Testing
;         */

;/////	WriteAddr 0x56000040,0x55555555
;	//WriteAddr 0x56000044,0xffffffff
;
;/**********************************************************************************/
	
;///////////////////////////////////////////////////////////////////////////////////


	BL	Main

	NOP
	NOP
	B	.
	END