?? al8051.vhd
字號(hào):
--------------------------------------------------------------------------------------
-- Copyright (c) 1999 by Alatek. All rights reserved.
--
-- DESIGN : AL8051
-- FILE NAME : AL8051.vhd
-- DESCRIPTION : Top Level
--
-- CREATED : 01/01/1999
-- MODIFIED :
-- VERSION : 1.0
-- AUTHOR : Anatoli Sergyienko, Volodymir Lepekha
-- HISTORY :
--------------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library work;
use work.registers.all;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- I/O wires of the I8051 are the following
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
entity AL8051 is
Port (
Port0: inout Std_Logic_Vector (7 downto 0);
Port1: inout Std_Logic_Vector (7 downto 0);
Port2: inout Std_Logic_Vector (7 downto 0);
Port3: inout Std_Logic_Vector (7 downto 0);
CLK: Std_Logic;
ALE: out Std_Logic;
PSEN: out Std_Logic;
EA: in Std_Logic;
RST: Std_Logic
);
end AL8051;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
architecture AL8051_ARCH of AL8051 is
signal y,y1,x,z,h,h1,yk,ht,ht1,pop,pop1,popp,ht1p : Integer range 0 to 65535;
-- type BYTE1 is array (0 to 255) of Bit_Vector (7 downto 0);
-- type BYTE2 is array (0 to 1023) of Bit_Vector (7 downto 0);
type VEC is array (4 downto 0) of Integer range 0 to 100;
signal DRAM: RAMemo;
signal PCBus,zo,zo1,zo2,zo3,zcom,zcom1:Bit_Vector (7 downto 0);
signal SMOD,SBUFs,SBUF1,SCONs,SCON1:Bit_Vector (7 downto 0);
signal zox: Bit_Vector(0 to 2);
signal z1,u,u1,u1k,u12,u2,u3,u4,u5,u6,z2,zvp,z11,z12,flz2,ft: Bit;
signal utt,utt1,utt1p,ut0,ut1,ut2,ut3,fal0,fal1,fal2,fal3: Bit;
signal PRP0,PRP1,PRP00,PRP01,PRP02,PRP03,PRP04,PRP05: Bit;
signal SDR,SDR1,zpp,strb:Bit;
signal q1,q2,q3: Std_Logic;
signal p5,p50,p51:Bit_Vector (4 downto 0);
signal TMODs,TCONs,TL0s,TH0s,TL1s,TH1s,Accumulator,PSWs: Bit_Vector (7 downto 0);
signal TCONa,TL0a,TH0a,TL1a,TH1a,dcom,ACOM: Bit_Vector (7 downto 0);
signal ppp: Bit_Vector (15 downto 0);
signal ttt:Std_Logic_Vector (7 downto 0);
signal tt0:Std_Logic_Vector (7 downto 0);
signal pp3: Bit_Vector (1 downto 0);
signal zbuf,zpos,zsdv,zpp1,zpp2,start,zh,zh1,outact: Bit;
signal PRT1,TFP,TFP1,TFP1p,PRR1,PB,RB1,SC2: Bit;
signal PRBit,PRBit1,flpp,flpp0,flpp1,fr: Bit;
signal flp0,flp1,flp2,flp3,CLKu,CYCLE : Bit;
signal larger: Std_Logic;
signal BUP0,BUP1,BUP2,BUP3: Bit_Vector (7 downto 0);
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- this is a program ROM
-- in file IPMemory.vhd
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
component IPMemory
Port (
i: in Integer range 0 to 65535; --address
PCBus: inout Bit_Vector (7 downto 0); --data
z: in Bit; --
z1: in Bit
);
end component;
component console
Port (
qq: in RAMemo;
BYTE1: in Bit_Vector (7 downto 0);
com: in Bit_Vector (7 downto 0);
r_TCON: in Bit_Vector (7 downto 0);
r_SCON: in Bit_Vector (7 downto 0);
r_TH0: in Bit_Vector (7 downto 0);
r_TL0: in Bit_Vector (7 downto 0);
r_TH1: in Bit_Vector (7 downto 0);
r_TL1: in Bit_Vector (7 downto 0);
r_bp0: in Bit_Vector (7 downto 0);
r_bp1: in Bit_Vector (7 downto 0);
r_bp2: in Bit_Vector (7 downto 0);
r_bp3: in Bit_Vector (7 downto 0);
y : in Integer
);
end component;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- this is a Timer Unit of MCS51
--
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
component Timer is
Port (
l0: in Bit_Vector (7 downto 0);
h0: in Bit_Vector (7 downto 0);
l1: in Bit_Vector (7 downto 0);
h1: in Bit_Vector (7 downto 0);
l0a: out Bit_Vector (7 downto 0);
h0a: out Bit_Vector (7 downto 0);
l1a: out Bit_Vector (7 downto 0);
h1a: out Bit_Vector (7 downto 0);
TCONa: out Bit_Vector (7 downto 0);
TMOD: in Bit_Vector (7 downto 0);
TCON: in Bit_Vector (7 downto 0);
Port3: in Std_Logic_Vector (7 downto 0);
s: in Bit;
TFP: out Bit
);
end component;
begin
--^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Switshing memory and timers
--^^^^^^^^^^^^^^^^^^^^^^^^^^^
UPP: IPMemory
Port map (
i => y, --address
PCBus => PCBus, --data
z => zh, -- output data event
z1 => zh1 --addres latch event
);
UUW: console
Port map(
qq => dram,
BYTE1 => ZCOM1,
com => dcom,
r_TCON => TCONa,
r_SCON => SCONs,
r_TH0 => TH0a,
r_TL0 => TL0a,
r_TH1 => TH1a,
r_TL1 => TL1a,
r_bp0 => bup0,
r_bp1 => bup1,
r_bp2 => bup2,
r_bp3 => bup3,
y => y
);
UT: Timer
Port map (
TMOD => TMODs,
l0 => TL0s,
h0 => TH0s,
l1 => TL1s,
h1 => TH1s,
TCON => TCONs,
l0a => TL0a,
h0a => TH0a,
l1a => TL1a,
h1a => TH1a,
TCONa => TCONa,
Port3 => Port3,
s => z1,
TFP => TFP
);
--^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Decoding machine cycles,
-- Reset
--^^^^^^^^^^^^^^^^^^^^^^^^^^^
process (CLK)
begin
CLKu <=to_bit(CLK);
end process;
CLK_dc: process (CLKu,rst)
variable a: Bit := '0';
begin
if ht = 23 then ht <= 0;
else ht <= ht +1;
end if;
if ht = 0 then utt <= not utt; end if;
if ht = 10 then ut3 <= not ut3; end if;
if ht = 20 then ut0 <= not ut0; end if;
if ht = 21 then ut1 <= not ut1; end if;
if ht = 22 then ut2 <= not ut2; end if;
-- h- machine phase =0...11
if h = 11 then h <= 0; else h <= h+1; end if;
-- ui - machine phases =0, 1
-- two times slower THan h
if h = 10 then u <= not u; end if;
if h = 1 then u12 <= not u12; end if;
if h = 2 then u2 <= not u2; end if;
if h = 3 then u3 <= not u3; end if;
if h = 4 then u4 <= not u4; end if;
if h = 8 then u5 <= not u5; end if;
if h = 9 then u6 <= not u6; end if;
if h = 2 then PSEN <= '1'; end if; --PSEN
if flz2 = '0' and fr = '1' then
if h = 8 then
PSEN <= '0'; end if;
end if;
if flz2 = '0' then
if h = 2 then
ALE <= '1'; end if; --ALE
end if;
if h = 6 then ALE <= '0'; end if;
u1 <=to_bit(RST); --u1 = Reset
if u1k = '1' then
ALE <= '1';
PSEN <= '1';
end if;
end process CLK_dc;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Input outer Interrupt signals
-- through Port3(2) and Port 3(3)
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
process (Port3(2),PRP00) -- INT0
variable a: Bit;
begin
if Port3(2) = '0' then
PRP0 <= '1';
else PRP0 <= '0';
end if;
if a /= PRP00 then PRP0 <= '0'; end if;
a:= PRP00;
end process;
process (Port3(3),PRP01) -- INT1
variable a: Bit;
begin
if Port3(3) = '0' then
PRP1 <= '1';
else PRP1 <= '0';
end if;
if a /= PRP01 then PRP1 <= '0'; end if;
a:= PRP01;
end process;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- the main process
-- of the I8051 processor kernel
--
-- there are some procedures
-- which work only in this process
-- and use this process variables
-- as side effects
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
kernel: process
variable pCLK,s,bank,fpr,fpru,j,k1,k2: Integer range -300 to 65663 := 0;
variable si,sti,ik,k,ik1,kk,jk: Integer range -300 to 65663 := 0;
variable PR,pr0,pr1,pr10,prp,pr111,ccom:Bit_Vector (7 downto 0);
-- variable com :Bit_Vector (7 downto 0);
variable pr2:Bit_Vector (15 downto 0);
variable pr3:Bit_Vector (3 downto 0);
variable pr4:Bit_Vector (2 downto 0);
variable pr5:Bit_Vector (4 downto 0);
variable pr6:Bit_Vector (6 downto 0);
variable pr50,pr51:Bit_Vector (4 downto 0);
variable fl0,fl1,flint,flint1: Bit;
variable ff,ffc,b,b1,b2,b3,b4,b5,ff1b:Bit := '0';
variable G0,G1,CT0,CT1,M00,M01,M10,M11:Bit := '0';
variable FBit,TR0,TR1,TF0,TF1,INT0,INT1,T0,T1:Bit := '0';
variable ADBit:Bit_Vector (255 downto 0);
variable BUFP0,BUFP1,BUFP2,BUFP3: Bit_Vector (7 downto 0);
Variable addrhi: Bit_Vector (7 downto 0);
variable pre: bit;
variable adp: integer;
variable fli: bit;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- this procedure returns <k1>
-- -Integer value of the byte Vector <com>
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure Proc2 -- byte ==> Integer
(variable k1 : out Integer range 0 to 255;
variable com1 : in Bit_Vector (7 downto 0) )
is
variable k11 : Integer range 0 to 255;
variable com11 : Bit_Vector (7 downto 0);
begin
com11 := com1; k11:=0;
for j in 7 downto 0 loop
k11:=2*k11;
if com11(j) = '1' then
k11:=k11+1;
end if;
end loop;
k1:= k11;
end procedure Proc2;
---^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- this procedure returns the byte Vector <com1>
-- -representation of the Integer<k1>
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure Proc3 -- Integer ==> byte
(variable k1 : in Integer range 0 to 255;
variable com1 : out Bit_Vector (7 downto 0) )
is
variable t,k11 : Integer range 0 to 255;
variable com11 : Bit_Vector (7 downto 0);
begin
k11:= k1; t:=128;
for j in 7 downto 0 loop
if k11 < t then com11(j) := '0';
else com11(j) := '1'; k11 := k11 - t;
end if;
t := t/2;
end loop;
com1 := com11;
end procedure Proc3;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- this procedure returns <k1>
-- -Integer value of a half word Vector <com1>
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure Proc21 -- 2 byte ==> Integer
(variable k1 : out Integer range 0 to 65535;
variable com1 : in Bit_Vector (15 downto 0) )
is
variable k11 : Integer range 0 to 65535;
variable com11 : Bit_Vector (15 downto 0);
begin
com11 := com1; k11:=0;
for j in 15 downto 0 loop
k11:=2*k11;
if com11(j) = '1' then k11:=k11+1; end if;
end loop;
k1:= k11;
end procedure Proc21;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- this procedure returns the halphword Vector <com1>
-- -representation of the Integer<k1>
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure Proc31 -- Integer ==> 2 byte
(variable k1 : in Integer range 0 to 65536;
variable com1 : out Bit_Vector (15 downto 0))
is
variable t,k11 : Integer range 0 to 65536;
variable com11 : Bit_Vector (15 downto 0);
begin
k11:= k1; t:=32768;
for j in 15 downto 0 loop
if k11 < t then com11(j) := '0';
else com11(j) := '1'; k11 := k11 - t;
end if;
t := t/2;
end loop;
com1 := com11;
end procedure Proc31;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- this procedure returns byte <com>
-- -a following instruction byte
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure Proc1 is -- com := pc
variable a: Bit; -- flag (0 - vnutr./1 - vnesh.) PP
variable ih: Integer :=0;
begin
ik := (ik + 1) mod 32;
outact<='0';
ih := i;
if EA = '1'or EA='H' then
if i < 4095 then a := '0';
else a := '1'; ih := y; -- - 4096;
outact<='1';
end if;
else a := '1'; ih := y;
end if;
fr <= a;
if a = '0'then
wait on u2;
zh <= not zh; -- output data event IPMemory
wait for 0.5 ns;
for j in 0 to 7 loop
if PCBus(j) = '1' then com(j) := '1';
else com(j) := '0';
end if;
end loop;
zcom1 <= com;
wait on u4;
zh1 <= not zh1; --addres latch event IPMemory
wait for 0.5 ns;
wait on u;
else
BUFP0 := "11111111";
bup0 <= bufp0; wait for 1 ps;
y1 <= ih;
wait for 1 ns;
proc31(ih,pr2);
ppp <= pr2;
y1 <= ih;
wait on u2;
for j in 0 to 7 loop
if Port0(j) = '1' then com(j) := '1';
else com(j) := '0';
end if;
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