?? al8051.vhd
字號:
begin
pr:= RAM(208);
pr0:= RAM(224);
y(0):=pr(7);
zo <= pr0;
zo1 <= l;
wait for 1 ns;
for t in 0 to 7 loop
x(0):= pr0(t);
x(1):= l(t);
x(2):= y(t);
case x is
when "000" => pr0(t):='0'; y(t+1):='0';
when "001" => pr0(t):='1'; y(t+1):='0';
when "010" => pr0(t):='1'; y(t+1):='1';
when "011" => pr0(t):='0'; y(t+1):='0';
when "100" => pr0(t):='1'; y(t+1):='1';
when "101" => pr0(t):='0'; y(t+1):='0';
when "110" => pr0(t):='0'; y(t+1):='1';
when "111" => pr0(t):='1'; y(t+1):='1';
end case;
end loop;
pr(6):=y(4);
pr(7):=y(8);
if y(7) = y(8) then pr(2):= '0';
else pr(2):= '1';
end if;
RAM(208):= pr;
RAM(224):= pr0;
end procedure subb;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Deriving relative addres
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure rel is
begin
proc2 (j,com);
ff:='1';
if j > 128 then i:= i+j - 256;
else i:=((i+j) mod 2**16);
end if;
if i < 0 then i:= 65535 + i;
end if;
end procedure rel;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Implementation DJNZ - instruction
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure djnz (l1: in Integer range 0 to 256 ) is
variable al1 : Integer range 0 to 266;
begin
al1 := l1;
dec_r(al1);
if RAM(al1) /= "00000000" then
Proc11;
rel;
ff:='0';
else Proc11;
end if;
end procedure djnz;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Implementation CJNE - instruction
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure cjne (l: in Bit_Vector (7 downto 0);
l1: in Bit_Vector (7 downto 0) ) is
variable a,b: Integer range 0 to 256;
variable al,al1: Bit_Vector (7 downto 0);
begin
al1 := l1;
al := l; -- if fli='0' then
if al1 /= al then
Proc11;
rel;
ff:='0';
else Proc11;
end if;
proc2(a,al1);
proc2(b,al);
if a > b then
ram(208):= ram(208) or "10000000";
else
ram(208):= ram(208) and "01111111";
end if;
-- end if; fli:='0';
end procedure cjne;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- implementation Port buffers p0..p4 and other registers
-- when reading-modification-writing
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure flag is
variable i:Integer range 0 to 10;
variable ren: Bit;
variable ip,cSCON:Bit_Vector (7 downto 0);
begin
ip := RAM(k);
for i in 0 to 7 loop
if ip(i) = '0' then
ttt(i) <= '0';
tt0(i) <= '0';
wait for 0.05 ns;
else
ttt(i) <= 'H';
tt0(i) <= 'Z';
wait for 0.05 ns;
end if;
end loop;
case k is
when 128 => Port0 <= tt0;
BUFP0 := RAM(k);
bup0 <= bufp0;
wait for 0.05 ns;
when 144 => Port1 <= ttt;
BUFP1 := RAM(k);
bup1 <= bufp1;
wait for 0.05 ns;
when 160 => Port2 <= ttt;
BUFP2 := RAM(k);
bup2 <= bufp2;
wait for 0.05 ns;
when 176 => bufp3 := ram(k);
pp3 <= bufp3(1 downto 0);
Port3 <= ttt;
wait for 0.05 ns;
BUFP3 := RAM(k);
bup3 <= bufp3;
wait for 0.05 ns;
when 153 => SBUFs <= RAM(153);
--## flag of sending ##
SDR <= not SDR;
SCONs <= RAM(152);
when 135 => SMOD <= RAM(135);
when 136 => TCONs <= RAM(136);
when 152 => SCONs <= RAM(152);
cSCON:= RAM(152);
ren:= (not cSCON(0)) and cSCON(4);
--## flag of receiving of edge R1 ##
if ren='1' then
SDR1 <= not SDR1;
end if;
when others =>
end case;
pp3<=bufp3(1 downto 0);
wait for 0.05 ns;
end procedure flag;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Exchange 4 lower Bits in ACC and RAM cell
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure xchd (l1: in Integer range 0 to 2 ) is
begin
proc2(k,RAM(bank+l1));
pr:=RP(k);--RAM(k);
pr0:=RAM(224);
pr1(3 downto 0):= pr(3 downto 0);
pr(3 downto 0):= pr0(3 downto 0);
pr0(3 downto 0):= pr1(3 downto 0);
RAM(k):= pr;
RAM(224):=pr0;
flag;
end procedure xchd;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Output to Ports and copy BitRAM to RAM
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure Bit_ram is
variable j,i,k1:Integer range 0 to 300;
variable ip:Bit_Vector (7 downto 0);
begin
i:= 0;
for k1 in 32 to 47 loop
RAM(k1):= ADBit(i+7 downto i);
i := i+8;
end loop;
k1:= 128;
for j in 0 to 15 loop
RAM(k1):= ADBit(i+7 downto i);
i := i+8;
k1 := k1+8;
end loop;
if flp0 = '1' then
ip := RAM(128);
for i in 0 to 7 loop
if ip(i) = '0' then
Port0(i) <= '0';
wait for 0.1 ns;
else Port0(i) <= 'Z';
wait for 0.1 ns;
end if;
end loop;
k := 128;
flag;
end if;
if flp1 = '1' then
ip := RAM(144);
for i in 0 to 7 loop
if ip(i) = '0' then
Port1(i) <= '0';
wait for 0.1 ns;
else Port1(i) <= 'H';
wait for 0.1 ns;
end if;
end loop;
k := 144;
flag;
end if;
if flp2 = '1' then
ip := RAM(160);
for i in 0 to 7 loop
if ip(i) = '0' then
Port2(i) <= '0';
wait for 0.1 ns;
else Port2(i) <= 'H';
wait for 0.1 ns;
end if;
end loop;
k := 160;
flag;
end if;
if flp3 = '1' then
ip := RAM(176);
for i in 0 to 7 loop
if ip(i) = '0' then
Port3(i) <= '0';
wait for 0.1 ns;
else Port3(i) <= 'H';
wait for 0.1 ns;
end if;
end loop;
k := 176;
flag;
end if;
flp0 <= '0';
flp1 <= '0';
flp2 <= '0';
flp3 <= '0';
end procedure Bit_ram;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Copy Byte memory to Bit memory
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure ram_Bit is
variable j,i,k:Integer range 0 to 300;
begin
i:= 0;
for k in 32 to 47 loop
ADBit(i+7 downto i):= RAM(k);
i := i+8;
end loop;
k:= 128;
for j in 0 to 15 loop
ADBit(i+7 downto i):=RAM(k);
i := i+8;
k := k+8;
end loop;
end procedure ram_Bit;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Initialization
-- after RESET
-- Case of I8051-I8031:
-- inner or outer Data RAM addresses 0...4095
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure prnach is
begin
while rst = '1' loop
fr <= '0';
u1k <= '1';
wait for 1 ps;
i:= 0;
ik:= 0;
for j in 0 to 255 loop
RAM(j):= "00000000";
end loop;
RAM(129):= "00000111"; -- SP <= 08H top of stack;
RAM(128):= "11111111";
RAM(144):= "11111111";
RAM(160):= "11111111";
RAM(176):= "11111111";
BUFP0 := "11111111";
bup0 <= bufp0;
wait for 0.05 ns;
BUFP1 := "11111111";
bup1 <= bufp1;
wait for 0.05 ns;
BUFP2 := "11111111";
bup2 <= bufp2;
wait for 0.05 ns;
BUFP3 := "11111111";
bup3 <= bufp3;
wait for 0.05 ns;
prp := "11111111";
pp3<="11";
wait for 0.05 ns;
Ram_Bit;
ttt <= "HHHHHHHH";
tt0<="ZZZZZZZZ";
Port0 <= tt0; --"ZZZZZZZZ";
Port1 <= ttt; --"HHHHHHHH";
Port2 <= ttt; --"HHHHHHHH";
Port3 <= ttt; --"HHHHHHHH";
wait for 0.1 ns;
end loop;
u1k <= '0';
wait on u;
y <= i;
wait for 0.1 ns;
tajm;
Proc1;
ik := 0;
end procedure prnach;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Timer and other interrupt control
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure obrab (v: in VEC;
i1: inout Integer range 0 to 7 )
is
variable pr :Bit_Vector (7 downto 0);
variable i11 :Integer range 0 to 7;
begin
i11:= i1;
pr := RAM(136);
i:=si;
call;
i:= V(i11); --interrupt vector
fli:='1'; --zapret raboty s i
if pr(0) = '1' then
if i11 = 4 then
RAM(136) := RAM(136) and "11111101";
PRP00 <= not PRP00;
end if;
end if;
if i11 = 3 then
RAM(136) := RAM(136) and "11011111";
end if;
if pr(2) = '1' then
if i11 = 2 then
RAM(136) := RAM(136) and "11110111";
PRP01 <= not PRP01;
end if;
end if;
if i11 = 1 then
RAM(136) := RAM(136) and "01111111";
end if;
i1 := 0;
TCONs<= RAM(136);
wait for 0.01 ns;
tajm;
y <= i;
wait on u;
-- ## 1** begin
TCONs <= RAM(136);
wait for 0.01 ns;
tajm;
y <= i;
wait for 0.5ns;
Proc1;
com1 := "10100101"; --This for invalid instruction test
TCONs <= RAM(136);
wait for 0.01 ns;
-- ## 1** end
--## interrupt flag set to serve 1 instruction ##
flint1 := '1';
end procedure obrab;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Interrupt Control
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
procedure interrup is
variable pr0,pr1,pr2,pr3:Bit_Vector (7 downto 0);
variable v : VEC;
variable j1,i1: Integer range -2 to 7;
variable m : Bit;
begin
pr0 := RAM(136);
pr1 := "11111111";
for j1 in 0 to 7 loop
if Port3(j1) = '0' then
pr1(j1) := '0';
end if;
if Port3(j1) = '1' or Port3(j1) = 'H' then
pr1(j1) := '1';
end if;
end loop;
if pr0(0) = '1' then pr0(1) := prp0;
else pr0(1) := not pr1(2);
end if;
if pr0(2) = '1' then pr0(3) := prp1;
else pr0(3) := not pr1(3);
end if;
RAM(136) := pr0 or ram(136) ;
V(4) := 3;
V(3) := 11;
V(2) := 19;
V(1) := 27;
V(0) := 35;
pr0:= RAM(184); -- IP prioritat reg B8h
pr1:= RAM(136); -- TCON of Timer 88h
pr2:= RAM(152); -- SCON of serial Port 98h
pr3:= RAM(168); -- IE interrupt mask reg. A8h
TCONs <= RAM(136);
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