?? al8051.vhd
字號:
SCONs <= RAM(152);
wait for 1 ns;
if pr3(7) = '1' then
pr5(4):= pr1(1);
pr5(3):= pr1(5);
pr5(2):= pr1(3);
pr5(1):= pr1(7);
pr5(0):= pr2(0) or pr2(1);
else
pr5 := "00000";
end if;
pr50 := "00000";
pr51 := "00000";
for i1 in 0 to 4 loop
if pr3(i1) = '1' then
if pr0(i1) = '1' then
pr51(4 - i1):=pr5(4 - i1);
else
pr50(4 - i1):=pr5(4 - i1);
end if;
end if;
end loop;
if fl1 = '0' then i1 := 4;
else i1 := -1;
end if;
while i1 /= -1 loop
if pr51(i1) = '1' then
obrab(V,i1);
fl1 := '1';
i1 := -1;
else i1:= i1 -1;
end if;
end loop;
if fl1 = '0' then
if fl0 = '0' then i1 := 4;
else i1 := -1;
end if;
else i1 := -1;
end if;
while i1 /= -1 loop
if pr50(i1) = '1' then
obrab(V,i1); --interrupt control
fl0 := '1';
i1 := -1;
else i1:= i1 -1;
end if;
end loop;
end procedure interrup;
--######################################################
-- Beginning of the I8051 kernel simulation process
--######################################################
begin
start <= '1';
fli:='0'; --enable raboty s i
wait for 0.01 ns;
while u1 = '1' loop
prnach;
end loop;
psws <=RAM(208);
wait for 0.1 ns;
if psws(4) = '0' then
if psws(3) = '0' then
bank := 0;
else bank := 8;
end if;
else
if psws(3) = '0' then
bank := 16;
else bank := 24;
end if;
end if;
x <= bank;
wait for 0.1 ns;
-- ## PRP03 i PRT1 form interrupt signal T1 after transmit ## --
-- after transmit PRT1 <= '1';
PRP03 <= '0';
if PRT1 = '1' then
RAM(152):= RAM(152) or "00000010";
PRP03 <= '1';
end if;
-- ## PRP04 i PRR1 form interrupt signal R1 after receive ## --
-- after receive PRR1 <= '1';
PRP04 <= '0';
if PRR1 = '1' then
RAM(152):= RAM(152) or "00000001";
SCONs <= ram(152);
wait for 0.05 ns;
PRP04 <= '1';
end if;
-- ## ##--
CYCLE <= not CYCLE;
sti := i;
if i=65535 then i:=0; else i:=i+1; end if;
y <= i;
wait for 0.5ns;
tajm;
Proc1;
com1 := com; -- First instruction byte is OPCODE
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- decoder of 1 byte instructions
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
case com1 is
when "00000000" => ff1b:='1';
when "00000011" => ff1b:='1';
when "00010011" => ff1b:='1';
when "00000100" => ff1b:='1';
when "00010100" => ff1b:='1';
when "00100010" => ff1b:='1';
when "00110010" => ff1b:='1';
when "00100011" => ff1b:='1';
when "00110011" => ff1b:='1';
when "01110011" => ff1b:='1';
when "10010011" => ff1b:='1';
when "10000011" => ff1b:='1';
when "10100011" => ff1b:='1';
when "10000100" => ff1b:='1';
when "10100100" => ff1b:='1';
when "10100101" => ff1b:='1';
when "10110011" => ff1b:='1';
when "11000011" => ff1b:='1';
when "11000100" => ff1b:='1';
when "11010011" => ff1b:='1';
when "11010100" => ff1b:='1';
when "11100000" => ff1b:='1';
when "11100100" => ff1b:='1';
when "11110000" => ff1b:='1';
when "11110100" => ff1b:='1';
when "11110010" => ff1b:='1';
when "11110011" => ff1b:='1';
when "11100010" => ff1b:='1';
when "11100011" => ff1b:='1';
when "00000110" => ff1b:='1';
when "00000111" => ff1b:='1';
when "00010110" => ff1b:='1';
when "00010111" => ff1b:='1';
when "00100110" => ff1b:='1';
when "00100111" => ff1b:='1';
when "00110110" => ff1b:='1';
when "00110111" => ff1b:='1';
when "01000110" => ff1b:='1';
when "01000111" => ff1b:='1';
when "01010110" => ff1b:='1';
when "01010111" => ff1b:='1';
when "01100110" => ff1b:='1';
when "01100111" => ff1b:='1';
when "10010110" => ff1b:='1';
when "10010111" => ff1b:='1';
when "11000110" => ff1b:='1';
when "11000111" => ff1b:='1';
when "11010110" => ff1b:='1';
when "11010111" => ff1b:='1';
when "11100110" => ff1b:='1';
when "11100111" => ff1b:='1';
when "11110110" => ff1b:='1';
when "11110111" => ff1b:='1';
when "11001000" => ff1b:='1';
when "11001001" => ff1b:='1';
when "11001010" => ff1b:='1';
when "11001011" => ff1b:='1';
when "11001100" => ff1b:='1';
when "11001101" => ff1b:='1';
when "11001110" => ff1b:='1';
when "11001111" => ff1b:='1';
when "10011000" => ff1b:='1';
when "10011001" => ff1b:='1';
when "10011010" => ff1b:='1';
when "10011011" => ff1b:='1';
when "10011100" => ff1b:='1';
when "10011101" => ff1b:='1';
when "10011110" => ff1b:='1';
when "10011111" => ff1b:='1';
when "01101000" => ff1b:='1';
when "01101001" => ff1b:='1';
when "01101010" => ff1b:='1';
when "01101011" => ff1b:='1';
when "01101100" => ff1b:='1';
when "01101101" => ff1b:='1';
when "01101110" => ff1b:='1';
when "01101111" => ff1b:='1';
when "00001000" => ff1b:='1';
when "00001001" => ff1b:='1';
when "00001010" => ff1b:='1';
when "00001011" => ff1b:='1';
when "00001100" => ff1b:='1';
when "00001101" => ff1b:='1';
when "00001110" => ff1b:='1';
when "00001111" => ff1b:='1';
when "00011000" => ff1b:='1';
when "00011001" => ff1b:='1';
when "00011010" => ff1b:='1';
when "00011011" => ff1b:='1';
when "00011100" => ff1b:='1';
when "00011101" => ff1b:='1';
when "00011110" => ff1b:='1';
when "00011111" => ff1b:='1';
when "01001000" => ff1b:='1';
when "01001001" => ff1b:='1';
when "01001010" => ff1b:='1';
when "01001011" => ff1b:='1';
when "01001100" => ff1b:='1';
when "01001101" => ff1b:='1';
when "01001110" => ff1b:='1';
when "01001111" => ff1b:='1';
when "01011000" => ff1b:='1';
when "01011001" => ff1b:='1';
when "01011010" => ff1b:='1';
when "01011011" => ff1b:='1';
when "01011100" => ff1b:='1';
when "01011101" => ff1b:='1';
when "01011110" => ff1b:='1';
when "01011111" => ff1b:='1';
when "00101000" => ff1b:='1';
when "00101001" => ff1b:='1';
when "00101010" => ff1b:='1';
when "00101011" => ff1b:='1';
when "00101100" => ff1b:='1';
when "00101101" => ff1b:='1';
when "00101110" => ff1b:='1';
when "00101111" => ff1b:='1';
when "00111000" => ff1b:='1';
when "00111001" => ff1b:='1';
when "00111010" => ff1b:='1';
when "00111011" => ff1b:='1';
when "00111100" => ff1b:='1';
when "00111101" => ff1b:='1';
when "00111110" => ff1b:='1';
when "00111111" => ff1b:='1';
when "11101000" => ff1b:='1';
when "11101001" => ff1b:='1';
when "11101010" => ff1b:='1';
when "11101011" => ff1b:='1';
when "11101100" => ff1b:='1';
when "11101101" => ff1b:='1';
when "11101110" => ff1b:='1';
when "11101111" => ff1b:='1';
when "11111000" => ff1b:='1';
when "11111001" => ff1b:='1';
when "11111010" => ff1b:='1';
when "11111011" => ff1b:='1';
when "11111100" => ff1b:='1';
when "11111101" => ff1b:='1';
when "11111110" => ff1b:='1';
when "11111111" => ff1b:='1';
when others => if i=65535 then i:=0; else i:=i+1; end if;
ff1b:= '0';
end case;
case com1 is
when "11100010" =>
when "11100011" =>
when "11110010" =>
when "11110011" =>
when "11100000" =>
when "11110000" =>
when others =>
y <= i;
wait for 0.5ns;
tajm;
Proc1;
end case;
flint := '0';
--## forj RETI ##
if com1 = "00110010" then flint := '1'; end if;
--## for Bit instructions ##
pr3(3 downto 1):= com(7 downto 5);
pr3(0):= com(3);
case com1 is
when "11000010" => if pr3 = "1011" then flint := '1'; end if;
when "11010010" => if pr3 = "1011" then flint := '1'; end if;
when "10110010" => if pr3 = "1011" then flint := '1'; end if;
when "10010010" => if pr3 = "1011" then flint := '1'; end if;
when others =>
end case;
--## for byte processing instructions ##
pr6(6 downto 4):= com(7 downto 5);
pr6(3 downto 0):= com(3 downto 0);
pr5:= com(7 downto 3);
if pr5 = "10001" then
if pr6 = "1011000" then
flint := '1';
end if;
end if;
dcom <= com1;
wait for 0.05 ns;
case com1 is
when "11110101" => if pr6 = "1011000" then flint := '1'; end if;
when "01110101" => if pr6 = "1011000" then flint := '1'; end if;
when "10000101" => if pr6 = "1011000" then flint := '1'; end if;
when "10000110" => if pr6 = "1011000" then flint := '1'; end if;
when "10000111" => if pr6 = "1011000" then flint := '1'; end if;
when "11000101" => if pr6 = "1011000" then flint := '1'; end if;
when "11000110" => if pr6 = "1011000" then flint := '1'; end if;
when "11000111" => if pr6 = "1011000" then flint := '1'; end if;
when "11010110" => if pr6 = "1011000" then flint := '1'; end if;
when "11010111" => if pr6 = "1011000" then flint := '1'; end if;
when others =>
end case;
if flint1 = '1' then flint := '1'; flint1 := '0'; end if;
if flint = '0' then
if ff = '1' then
ff:='0';
si := sti;
else
si := sti;
end if;
interrup; --interrupt control
end if;
-- ## loading SCON into RAM ##
RAM(153):= SBUF1;
if flpp = '1' then
SCONs(2) <= sc2;
if sc2 = '0' then
RAM(152):= RAM(152) and "11111011";
else RAM(152):= RAM(152) or "00000100";
end if;
flpp1 <= not flpp1;
end if;
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-- Main instruction decoder
--
--^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
case com1 is
when "00000000" => j:=j; -- NOP
when "00000001" => ajmp("00000000000"); -- AJMP 000+ad 8
when "00000010" => ljmp; -- LJMP ad 16
when "00000011" => -- RR A 1 b.
pr := RAM(224);
pr1(6 downto 0):=pr(7 downto 1);
pr1(7):=pr(0);
RAM(224):=pr1;
when "00000100" => inc_r(224); -- INC A 1 b.
when "00000101" => -- INC ad 2 b.
proc2 (j,com);
if j = 128 then RAM(128):= BUFP0; end if;
if j = 144 then RAM(144):= BUFP1; end if;
if j = 160 then RAM(160):= BUFP2; end if;
if j = 176 then RAM(176):= BUFP3; end if;
inc_r(j);
k := j;
flag;
when "00000110" => -- INC @R0 1 b.
proc2(j,RAM(bank+0));
if j = 128 then RAM(128):= BUFP0; end if;
if j = 144 then RAM(144):= BUFP1; end if;
if j = 160 then RAM(160):= BUFP2; end if;
if j = 176 then RAM(176):= BUFP3; end if;
inc_r(j);
k := j;
flag;
when "00000111" => -- INC @R1 1 b.
proc2(j,RAM(bank+1));
if j = 128 then RAM(128):= BUFP0; end if;
if j = 144 then RAM(144):= BUFP1; end if;
if j = 160 then RAM(160):= BUFP2; end if;
if j = 176 then RAM(176):= BUFP3; end if;
inc_r(j);
k := j;
flag;
when "00010000" => -- JBC Bit,rel 3 b.
proc2 (k,com);
case com(7 downto 3) is
when "10000" => ADBit(135 downto 128) := BUFP0; flp0 <= '1';
when "10010" => ADBit(151 downto 144) := BUFP1; flp1 <= '1';
when "10100" => ADBit(167 downto 160) := BUFP2; flp2 <= '1';
when "10110" => ADBit(183 downto 176) := BUFP3; flp3 <= '1';
when others => flp0 <= '0'; flp1 <= '0'; flp2 <= '0'; flp3 <= '0';
end case;
Proc11;
if ADBit(k) = '1' then rel;
ADBit(k) := '0';
fBit := '1';
ff:='0';
end if;
when "00010001" => acall("00000000000"); -- ACALL 000+ad8 2 b.
when "00010010" => lcall; -- LCALL ad 16 3 b.
when "00010011" => -- RRC A 1 b.
pr := RAM(224);
pr0:= RAM(208);
pr1(6 downto 0):=pr(7 downto 1);
pr1(7):=pr0(7);
pr0(7):= pr(0);
RAM(224):=pr1;
RAM(208):=pr0;
when "00010100" => dec_r(224); -- DEC A 1 b.
when "00010101" => -- DEC ad 2 b.
proc2 (j,com);
if j = 128 then RAM(128):= BUFP0; end if;
if j = 144 then RAM(144):= BUFP1; end if;
if j = 160 then RAM(160):= BUFP2; end if;
if j = 176 then RAM(176):= BUFP3; end if;
dec_r(j);
k := j;
flag;
when "00010110" => -- DEC @R0 1 b.
proc2(j,RAM(bank+0));
if j = 128 then RAM(128):= BUFP0; end if;
if j = 144 then RAM(144):= BUFP1; end if;
if j = 160 then RAM(160):= BUFP2; end if;
if j = 176 then RAM(176):= BUFP3; end if;
dec_r(j);
k := j;
flag;
when "00010111" => -- DEC @R1 1 b.
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