?? s3c2443.inc
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
;-------------------------------------------------------------------------------
;
; Header: s3c2443.inc
;
; This header file defines only those registers required by the startup
; code. All addresses are based off the physical addresses (PA) defined
; in s3c2443_base_reg.h (s3c2443_base_reg.inc).
;
;-------------------------------------------------------------------------------
; Include the base register definitions
INCLUDE s3c2443_base_regs.inc
;------------------------------------------------------------------------------
; General CPU constants
Mode_USR EQU (0x10)
Mode_FIQ EQU (0x11)
Mode_IRQ EQU (0x12)
Mode_SVC EQU (0x13)
Mode_ABT EQU (0x17)
Mode_UND EQU (0x1B)
Mode_SYS EQU (0x1F)
I_Bit EQU (0x80)
F_Bit EQU (0x40)
R1_iA EQU (1<<31)
R1_nF EQU (1<<30)
;------------------------------------------------------------------------------
; Miscellaneous defines
WORD_SIZE EQU (4)
DW8 EQU (0x0)
DW16 EQU (0x1)
DW32 EQU (0x2)
WAIT EQU (0x1<<2)
UBLB EQU (0x1<<3)
;------------------------------------------------------------------------------
; MMU constants
MMU_CTL_MASK EQU (0x3FFF0000)
MMU_TTB_MASK EQU (0x00003FFF)
MMU_ID_MASK EQU (0xFFFFFFF0)
;------------------------------------------------------------------------------
; Interrupt Control Registers
INTMSK EQU (S3C2443_BASE_REG_PA_INTR + 0x08)
INTSUBMSK EQU (S3C2443_BASE_REG_PA_INTR + 0x1C)
INTMOD EQU (S3C2443_BASE_REG_PA_INTR + 0x04)
INTPND EQU (S3C2443_BASE_REG_PA_INTR + 0x10)
SRCPND EQU (S3C2443_BASE_REG_PA_INTR + 0x00)
vSRCPND EQU 0xB0C00000 ;Interrupt request status
vINTMOD EQU 0xB0C00004 ;Interrupt mode control
vINTMSK EQU 0xB0C00008 ;Interrupt mask control
vPRIORITY EQU 0xB0C0000C ;IRQ priority control
vINTPND EQU 0xB0C00010 ;Interrupt request status
vINTOFFSET EQU 0xB0C00014 ;Interruot request source offset
vSUBSRCPND EQU 0xB0C00018 ;Sub source pending
vINTSUBMSK EQU 0xB0C0001C ;Interrupt sub mask
vINTBASE EQU 0xB0C00000 ;Interrupt request status
oSRCPND EQU 0x00 ;Interrupt request status
oINTMSK EQU 0x08 ;Interrupt mask control
oINTPND EQU 0x10 ;Interrupt request status
oINTSUBMSK EQU 0x1C ;Interrupt sub mask
;------------------------------------------------------------------------------
; IOPort Control Registers
GPACDL EQU (S3C2443_BASE_REG_PA_IOPORT + 0x00)
GPACDH EQU (S3C2443_BASE_REG_PA_IOPORT + 0x04)
GPBCON EQU (S3C2443_BASE_REG_PA_IOPORT + 0x10)
GPBDAT EQU (S3C2443_BASE_REG_PA_IOPORT + 0x14)
GPBUDP EQU (S3C2443_BASE_REG_PA_IOPORT + 0x18)
GPFCON EQU (S3C2443_BASE_REG_PA_IOPORT + 0x50)
GPFDAT EQU (S3C2443_BASE_REG_PA_IOPORT + 0x54)
GPFUDP EQU (S3C2443_BASE_REG_PA_IOPORT + 0x58)
GPHCON EQU (S3C2443_BASE_REG_PA_IOPORT + 0x70)
GPHDAT EQU (S3C2443_BASE_REG_PA_IOPORT + 0x74)
GPHUDP EQU (S3C2443_BASE_REG_PA_IOPORT + 0x78)
GPKCON EQU (S3C2443_BASE_REG_PA_IOPORT + 0xE0)
GPKDAT EQU (S3C2443_BASE_REG_PA_IOPORT + 0xE4)
GPKUDP EQU (S3C2443_BASE_REG_PA_IOPORT + 0xE8)
MISCCR EQU (S3C2443_BASE_REG_PA_IOPORT + 0x80)
GSTATUS3 EQU (S3C2443_BASE_REG_PA_IOPORT + 0xB8)
vGPFCON EQU 0xB2100050 ;Port F data
vGPFDAT EQU 0xB2100054 ;Port F data
vGPFUDP EQU 0xB2100058 ;Port F data
vEINTMASK EQu 0XB21000A4
vEINTPEND EQU 0xB21000A8
vGPIOBASE EQU 0xB2100000 ;Port A control
oGSTATUS3 EQU 0xB8
oGPFCON EQU 0x50 ;Port F control
oGPFDAT EQU 0x54 ;Port F data
oGPFUDP EQU 0x58 ;Pull-Down control F
vMISCCR EQU 0xB2100080 ;Miscellaneous control
;------------------------------------------------------------------------------
; Watch Dog Control Registers
WTCON EQU (S3C2443_BASE_REG_PA_WATCHDOG + 0x00)
WTDAT EQU (S3C2443_BASE_REG_PA_WATCHDOG + 0x04)
WTCNT EQU (S3C2443_BASE_REG_PA_WATCHDOG + 0x08)
vWTCON EQU 0xB1E00000 ;Watch-dog timer mode
vWTDAT EQU 0xB1E00004 ;Watch-dog timer data
vWTCNT EQU 0xB1E00008 ;Eatch-dog timer count
;------------------------------------------------------------------------------
; Memory configuration Control Registers
BANKCFG EQU 0x48000000 ;;//Mobile DRAM configuration
BANKCON1 EQU 0x48000004 ;;//Mobile DRAM control
BANKCON2 EQU 0x48000008 ;;//Mobile DRAM timing control
BANKCON3 EQU 0x4800000C ;;//Mobile DRAM (E)MRS
REFRESH EQU 0x48000010 ;;//Mobile DRAM refresh control
TIMEOUT EQU 0x48000014 ;;//Write Buffer Time out control
vREFRESH EQU 0xB0800010 ;DRAM/SDRAM refresh
;//chapter1 EBI controller
EBICON EQU 0x4E800008 ;//Bank Configuration
;//chapter4 SSMC
SMBIDCYR0 EQU 0x4F000000 ;//Bank0 idle cycle control
SMBIDCYR1 EQU 0x4F000020 ;//Bank1 idle cycle control
SMBIDCYR2 EQU 0x4F000040 ;//Bank2 idle cycle control
SMBIDCYR3 EQU 0x4F000060 ;//Bank3 idle cycle control
SMBIDCYR4 EQU 0x4F000080 ;//Bank0 idle cycle control
SMBIDCYR5 EQU 0x4F0000A0 ;//Bank5 idle cycle control
SMBWSTRDR0 EQU 0x4F000004 ;//Bank0 read wait state control
SMBWSTRDR1 EQU 0x4F000024 ;//Bank1 read wait state control
SMBWSTRDR2 EQU 0x4F000044 ;//Bank2 read wait state control
SMBWSTRDR3 EQU 0x4F000064 ;//Bank3 read wait state control
SMBWSTRDR4 EQU 0x4F000084 ;//Bank4 read wait state control
SMBWSTRDR5 EQU 0x4F0000A4 ;//Bank5 read wait state control
SMBWSTWRR0 EQU 0x4F000008 ;//Bank0 write wait state control
SMBWSTWRR1 EQU 0x4F000028 ;//Bank1 write wait state control
SMBWSTWRR2 EQU 0x4F000048 ;//Bank2 write wait state control
SMBWSTWRR3 EQU 0x4F000068 ;//Bank3 write wait state control
SMBWSTWRR4 EQU 0x4F000088 ;//Bank4 write wait state control
SMBWSTWRR5 EQU 0x4F0000A8 ;//Bank5 write wait state control
SMBWSTOENR0 EQU 0x4F00000C ;//Bank0 output enable assertion delay control
SMBWSTOENR1 EQU 0x4F00002C ;//Bank1 output enable assertion delay control
SMBWSTOENR2 EQU 0x4F00004C ;//Bank2 output enable assertion delay control
SMBWSTOENR3 EQU 0x4F00006C ;//Bank3 output enable assertion delay control
SMBWSTOENR4 EQU 0x4F00008C ;//Bank4 output enable assertion delay control
SMBWSTOENR5 EQU 0x4F0000AC ;//Bank5 output enable assertion delay control
SMBWSTWENR0 EQU 0x4F000010 ;//Bank0 write enable assertion delay control
SMBWSTWENR1 EQU 0x4F000030 ;//Bank1 write enable assertion delay control
SMBWSTWENR2 EQU 0x4F000050 ;//Bank2 write enable assertion delay control
SMBWSTWENR3 EQU 0x4F000070 ;//Bank3 write enable assertion delay control
SMBWSTWENR4 EQU 0x4F000090 ;//Bank4 write enable assertion delay control
SMBWSTWENR5 EQU 0x4F0000B0 ;//Bank5 write enable assertion delay control
SMBCR0 EQU 0x4F000014 ;//Bank0 control
SMBCR1 EQU 0x4F000034 ;//Bank1 control
SMBCR2 EQU 0x4F000054 ;//Bank2 control
SMBCR3 EQU 0x4F000074 ;//Bank3 control
SMBCR4 EQU 0x4F000094 ;//Bank4 control
SMBCR5 EQU 0x4F0000B4 ;//Bank5 control
SMBSR0 EQU 0x4F000018 ;//Bank0 status
SMBSR1 EQU 0x4F000038 ;//Bank1 status
SMBSR2 EQU 0x4F000058 ;//Bank2 status
SMBSR3 EQU 0x4F000078 ;//Bank3 status
SMBSR4 EQU 0x4F000098 ;//Bank4 status
SMBSR5 EQU 0x4F0000B8 ;//Bank5 status
SMBWSTBRDR0 EQU 0x4F00001C ;//Bank0 burst read wait delay control
SMBWSTBRDR1 EQU 0x4F00003C ;//Bank1 burst read wait delay control
SMBWSTBRDR2 EQU 0x4F00005C ;//Bank2 burst read wait delay control
SMBWSTBRDR3 EQU 0x4F00007C ;//Bank3 burst read wait delay control
SMBWSTBRDR4 EQU 0x4F00009C ;//Bank4 burst read wait delay control
SMBWSTBRDR5 EQU 0x4F0000BC ;//Bank5 burst read wait delay control
SSMCSR EQU 0x4F000200 ;//SROMC status
SSMCCR EQU 0x4F000204 ;//SROMC control
;------------------------------------------------------------------------------
; Clock and Power Control Registers
LOCKCON0 EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x00)
LOCKCON1 EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x04)
MPLLCON EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x10)
EPLLCON EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x18)
HCLKCON EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x30)
PCLKCON EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x34)
SCLKCON EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x38)
CLKDIV0 EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x24)
CLKDIV1 EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x28)
CLKSRC EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x20)
PWRMODE EQU (S3C2443_BASE_REG_PA_CLOCK_POWER + 0x40)
RSTSTAT EQU 0x4C000068 ;//Reset status
WKUPSTAT EQU 0x4C00006c ;//Wakeup status
INFORM0 EQU 0x4C000070 ;//Sleep mode information 0
INFORM1 EQU 0x4C000074 ;//Sleep mode information 1
INFORM2 EQU 0x4C000078 ;//Sleep mode information 2
INFORM3 EQU 0x4C00007C ;//Sleep mode information 3
RSTCON EQU 0x4C000064 ;//Reset Control
vRSTSTAT EQU 0xb1000068 ;//Reset status
vWKUPSTAT EQU 0xb100006c ;//Wakeup status
vINFORM0 EQU 0xb1000070 ;//Sleep mode information 0
vINFORM1 EQU 0xb1000074 ;//Sleep mode information 1
vINFORM2 EQU 0xb1000078 ;//Sleep mode information 2
vINFORM3 EQU 0xb100007C ;//Sleep mode information 3
vHCLKCON EQU 0xb1000030 ;HCLK enable control
vPCLKCON EQU 0xb1000034 ;PCLK enable control
vSCLKCON EQU 0xb1000038 ;Special colck enable control
vCLKDIV0 EQU 0xb1000024 ;Clock divider control
vCLKDIV1 EQU 0xb1000028 ;Clock divider control
vRSTCON EQU 0xb1000064 ;Reset Control
vOSCSET EQU 0xb1000008 ;Osc Control
vPWRCFG EQU 0xb1000060 ;Power config Control
vPWRMODE EQU 0xb1000040 ;Power Mode Control
;---------------------------------------
; nGCS0 = AMD Flash = Bank0 Controller Parameter setting
;---------------------------------------
GBLL AMDBOOT ; bacnk0, 16-bit and flash
; GBLL NANDBOOT ; bacnk0, 8-bit nand
IF :DEF: AMDBOOT
IDCY0 EQU 0x0 ; Idle or turnaround cycles IDCY*HCLK
WSTRD0 EQU 0xe ; Read wait state = tacc
WSTWR0 EQU 0xe ; wrie wait state
WSTOEN0 EQU 0 ; output enable assertion delay from CS
WSTWEN0 EQU 0 ; write enable assertion delay
BlWriteEn EQU 1 ;bit21-SMBAA signal control:0-1at all times, 1 active for sync
AddrValidWriteEn EQU 1 ;bit20-SMADDRVALD during write:0-always high,1-active for write
BurstLenWrite EQU 0 ;bit1819-burst transfer length:0-4,1-8,3-continu(sync only)
SyncWriteDev EQU 0 ;bit17-0:async, 1:sync
BMWrite EQU 0 ;bit16-burt mode write : 0-non-burst, 1-burst
WrapRead EQU 0 ;bit14-0-disable, 1 enable
BlReadEn EQU 1 ;bit13-SMBAA signal :0-1 at all time, 1-active for sync read
AddrValidReadEn EQU 1 ;bit12-SMADDRVALID signal: 0-always HIGH, 1-active for async & sync read
BurstLenRead EQU 0 ;bit1011-burst transfer length:0-4,1-8,2-16,3-cont(sync only)
SyncReadDev EQU 0 ;bit9-sync access :0-async, 1-sync
BMRead EQU 0 ;bit8-burst mode red and async page mode
SMBLSPOL EQU 0 ;bit6-polarit of signal nSMBLS
MW EQU 1 ;bit45-memory width : 00-8bit,01-16bit,10-32bit
WP EQU 0 ;bit3-write protect
WaitEn EQU 0 ;bit2-external wait signal enable
WaitPol EQU 0 ;bit1-polarity of the external wait input for actiation
RBLE EQU 0 ;bit0-read byte lane enable
SMBCR0_0 EQU ((BMRead<<8)+(SMBLSPOL<<6)+(MW<<4)+(WP<<3)+(WaitEn<<2)+(WaitPol<<1)+RBLE)
SMBCR0_1 EQU ((WrapRead<<14)+(BlReadEn<<13)+(AddrValidReadEn<<12)+(BurstLenRead<<10)+(SyncReadDev<<9))
SMBCR0_2 EQU ((BlWriteEn<<21)+(AddrValidWriteEn<<20)+(BurstLenWrite<<18)+(SyncWriteDev<<17)+(BMWrite<<16))
WaitTourErr0 EQU 0 ; external wait timeout error flag
WSTBRD0 EQU 0x1f ; burst read wait state
MemClkRatio EQU 1 ; SMMEMCLK :0-HCLK,1-HCLK/2,2-HCLK/3
SMClockEn EQU 1 ; SMCLK enable 0-only active during mem access,1-always running
ELSE ; NAND Boot....
IDCY0 EQU 0x0 ; Idle or turnaround cycles IDCY*HCLK
WSTRD0 EQU 0xe ; Read wait state = tacc
WSTWR0 EQU 0xe ; wrie wait state
WSTOEN0 EQU 0 ; output enable assertion delay from CS
WSTWEN0 EQU 0 ; write enable assertion delay
BlWriteEn EQU 1 ;bit21-SMBAA signal control:0-1at all times, 1 active for sync
AddrValidWriteEn EQU 1 ;bit20-SMADDRVALD during write:0-always high,1-active for write
BurstLenWrite EQU 0 ;bit1819-burst transfer length:0-4,1-8,3-continu(sync only)
SyncWriteDev EQU 0 ;bit17-0:async, 1:sync
BMWrite EQU 0 ;bit16-burt mode write : 0-non-burst, 1-burst
WrapRead EQU 0 ;bit14-0-disable, 1 enable
BlReadEn EQU 1 ;bit13-SMBAA signal :0-1 at all time, 1-active for sync read
AddrValidReadEn EQU 1 ;bit12-SMADDRVALID signal: 0-always HIGH, 1-active for async & sync read
BurstLenRead EQU 0 ;bit1011-burst transfer length:0-4,1-8,2-16,3-cont(sync only)
SyncReadDev EQU 0 ;bit9-sync access :0-async, 1-sync
BMRead EQU 0 ;bit8-burst mode red and async page mode
SMBLSPOL EQU 0 ;bit6-polarit of signal nSMBLS
MW EQU 0 ;bit45-memory width : 00-8bit,01-16bit,10-32bit
WP EQU 0 ;bit3-write protect
WaitEn EQU 0 ;bit2-external wait signal enable
WaitPol EQU 0 ;bit1-polarity of the external wait input for actiation
RBLE EQU 0 ;bit0-read byte lane enable
SMBCR0_0 EQU ((BMRead<<8)+(SMBLSPOL<<6)+(MW<<4)+(WP<<3)+(WaitEn<<2)+(WaitPol<<1)+RBLE)
SMBCR0_1 EQU ((WrapRead<<14)+(BlReadEn<<13)+(AddrValidReadEn<<12)+(BurstLenRead<<10)+(SyncReadDev<<9))
SMBCR0_2 EQU ((BlWriteEn<<21)+(AddrValidWriteEn<<20)+(BurstLenWrite<<18)+(SyncWriteDev<<17)+(BMWrite<<16))
WaitTourErr0 EQU 0 ; external wait timeout error flag
WSTBRD0 EQU 0x1f ; burst read wait state
MemClkRatio EQU 1 ; SMMEMCLK :0-HCLK,1-HCLK/2,2-HCLK/3
SMClockEn EQU 1 ; SMCLK enable 0-only active during mem access,1-always running
ENDIF ; IF :DEF: AMDBOOT
;#########################################################################################
;#########################################################################################
_ISR_STARTADDRESS EQU 0x33ffff00
top_of_stacks EQU _ISR_STARTADDRESS
;=====================================================================================
; (42,1,1)=200Mhz, (47,1,1)=220Mhz, (72,2,1)=240Mhz, (57,1,1)=260Mhz, (125,4,1)=266Mhz
; (43,1,1)=204Mhz,
; (62,1,1)=280Mhz, (67,1,1)=300Mhz, (72,4,0)=320Mhz, (63,3,0)=340Mhz, (52,2,0)=360Mhz
; (42,1,0)=400Mhz,
; ========================================================================
; Decide Re-setting the PLL value and mem setting in Kernel.
; If 1, In Kernel the PLL will set PLL and Memory setting again.
; If 0, The kernel will not change PLL and memory,
; so The setting in Eboot will be used.
GBLA CHANGE_CLK_EBOOT
GBLA CHANGE_CLK_OAL
CHANGE_CLK_EBOOT SETA 1 ; 1:RE-Setting PLL value(refer startup.s in Eboot)
CHANGE_CLK_OAL SETA 1 ; 1:RE-Setting PLL value(refer startup.s in oal)
; ========================================================================
; PLL Value setting
; EBOOT and Kernel refers this value.
;=====================================================================================
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