?? firandmac.mdl
字號:
Model {
Name "firandmac"
Version 4.00
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines off
ShowLineDimensions off
ShowPortDataTypes off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovNameIncrementing off
CovHtmlReporting on
BlockNameDataTip off
BlockParametersDataTip on
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
PostLoadFcn "coef = [3 5 7 0]"
Created "Fri Jun 30 15:00:05 2000"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "Yongchun"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Sun Dec 16 23:36:41 2001"
ModelVersionFormat "1.%<AutoIncrement:134>"
ConfigurationManager "none"
SimParamPage "Solver"
StartTime "0.0"
StopTime "50"
SolverMode "Auto"
Solver "ode45"
RelTol "1e-3"
AbsTol "auto"
Refine "1"
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "auto"
MaxOrder 5
OutputOption "RefineOutputTimes"
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
LimitDataPoints off
MaxDataPoints "1000"
Decimation "1"
AlgebraicLoopMsg "warning"
MinStepSizeMsg "warning"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
InheritedTsInSrcMsg "warning"
SingleTaskRateTransMsg "none"
MultiTaskRateTransMsg "error"
IntegerOverflowMsg "warning"
CheckForMatrixSingularity "none"
UnnecessaryDatatypeConvMsg "none"
Int32ToFloatConvMsg "warning"
SignalLabelMismatchMsg "none"
LinearizationMsg "none"
VectorMatrixConversionMsg "none"
SfunCompatibilityCheckMsg "none"
BlockPriorityViolationMsg "warning"
ArrayBoundsChecking "none"
ConsistencyChecking "none"
ZeroCross on
Profile off
SimulationMode "normal"
RTWSystemTargetFile "grt.tlc"
RTWInlineParameters off
RTWRetainRTWFile off
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
TLCProfiler off
TLCDebug off
TLCCoverage off
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "oneshot"
ExtModeTrigPort "1"
ExtModeTrigElement "any"
ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect off
ExtModeLogAll on
OptimizeBlockIOStorage on
BufferReuse on
ParameterPooling on
BlockReductionOpt off
BooleanDataType off
BlockDefaults {
Orientation "right"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "firandmac"
Location [313, 83, 871, 299]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name " System Generator"
Tag "genX"
Ports []
Position [176, 130, 226, 182]
ShowName off
AttributesFormatString "System\\nGenerator"
SourceBlock "xbsBasic/ System Generator"
SourceType "Xilinx System Generator"
xilinxfamily "Virtex"
directory "c:/temp/firandmac11"
run_coregen off
core_generation "According to Block Masks"
dbl_ovrd "According to Block Masks"
testbench on
}
Block {
BlockType Reference
Name "Din"
Ports [1, 1]
Position [175, 79, 230, 101]
BackgroundColor "yellow"
SourceBlock "xbsIO/Gateway In"
SourceType "Xilinx Gateway In Block"
arith_type "Unsigned"
n_bits "16"
bin_pt "0"
quantization "Truncate"
overflow "Wrap"
period "length(coef)"
dbl_ovrd off
}
Block {
BlockType Reference
Name "Dout"
Ports [1, 1]
Position [395, 79, 450, 101]
BackgroundColor "yellow"
SourceBlock "xbsIO/Gateway Out"
SourceType "Xilinx Gateway Out Block"
}
Block {
BlockType Reference
Name "Dout MAC"
Ports [1, 1]
Position [395, 159, 450, 181]
BackgroundColor "yellow"
SourceBlock "xbsIO/Gateway Out"
SourceType "Xilinx Gateway Out Block"
}
Block {
BlockType Reference
Name "FIR"
Ports [1, 1]
Position [290, 64, 340, 116]
SourceBlock "xbsDSP/FIR"
SourceType "FIR Filter Block"
coef "coef"
structure "Inferred from Coefficients"
coef_n_bits "8"
coef_bin_pt "0"
coef_arith_type "Unsigned"
polyphase_behavior "Single Rate: sample in - sample out"
latency "4"
period "1"
explicit_period off
dbl_ovrd off
gen_core on
over_sample "4"
}
Block {
BlockType SubSystem
Name "MAC Based FIR"
Ports [1, 1]
Position [275, 150, 340, 190]
ShowPortLabels on
TreatAsAtomicUnit off
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
System {
Name "MAC Based FIR"
Location [195, 329, 1012, 601]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Inport
Name "Din"
Position [15, 173, 45, 187]
Port "1"
Interpolate on
}
Block {
BlockType Reference
Name "Circular Data Buffer"
Ports [3, 1]
Position [315, 146, 370, 214]
FontName "Arial"
SourceBlock "xbsMemory/Single Port RAM"
SourceType "Xilinx Single Port RAM Block"
depth "length(coef)"
initVector "zeros(1,length(coef))"
quantization "Truncate"
overflow "Wrap"
period "1"
explicit_period off
store_only_valid on
init_zero off
dbl_ovrd off
distributed_mem off
gen_core on
}
Block {
BlockType Reference
Name "Coef LUT"
Ports [1, 1]
Position [310, 45, 365, 85]
SourceBlock "xbsMemory/ROM"
SourceType "Xilinx Single Port ROM Block"
depth "length(coef)"
initVector "coef([1 length(coef):-1:2])"
n_bits "8"
bin_pt "0"
arith_type "Signed (2's comp)"
quantization "Round (unbiased: +/- Inf)"
overflow "Saturate"
period "1"
explicit_period off
init_zero on
dbl_ovrd off
distributed_mem off
gen_core on
}
Block {
BlockType SubSystem
Name "Controller"
Ports [0, 3]
Position [95, 56, 170, 104]
ShowPortLabels on
TreatAsAtomicUnit off
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
System {
Name "Controller"
Location [189, 319, 650, 576]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Reference
Name "Add"
Ports [2, 1]
Position [250, 28, 295, 72]
SourceBlock "xbsMath/AddSub"
SourceType "Xilinx Adder/Subtractor Block"
mode "Addition"
precision "User Defined"
arith_type "Unsigned"
n_bits "ceil(log2(length(coef)))"
bin_pt "0"
quantization "Truncate"
overflow "Wrap"
latency "0"
period "1"
explicit_period off
dbl_ovrd off
}
Block {
BlockType Reference
Name "Computation Rate Counter"
Ports [0, 1]
Position [50, 105, 95, 145]
Priority "5"
SourceBlock "xbsBasic/Counter"
SourceType "Xilinx Counter Block"
n_bits "ceil(log2(length(coef)))"
bin_pt "0"
arith_type "Unsigned"
period "1"
start_count "0"
cnt_to "inf"
cnt_by_val "1"
operation "Up"
dbl_ovrd off
gen_core on
}
Block {
BlockType Reference
Name "Relational"
Ports [2, 1]
Position [230, 173, 275, 217]
ShowName off
SourceBlock "xbsMath/Relational"
SourceType "Xilinx Relational Block"
mode "a=b"
latency "0"
period "1"
explicit_period off
dbl_ovrd off
use_core off
gen_core on
}
Block {
BlockType Reference
Name "Sample Rate Counter"
Ports [0, 1]
Position [50, 15, 95, 55]
Priority "5"
SourceBlock "xbsBasic/Counter"
SourceType "Xilinx Counter Block"
n_bits "ceil(log2(length(coef)))"
bin_pt "0"
arith_type "Unsigned"
period "length(coef)"
start_count "0"
cnt_to "inf"
cnt_by_val "1"
operation "Up"
dbl_ovrd off
gen_core on
}
Block {
BlockType Reference
Name "Up Sample"
Ports [1, 1]
Position [160, 17, 195, 53]
ShowName off
SourceBlock "xbsBasic/Up Sample"
SourceType "Xilinx Up Sampling Block"
sample_ratio "length(coef)"
copy_samples on
dbl_ovrd off
}
Block {
BlockType Reference
Name "Zero"
Ports [0, 1]
Position [160, 195, 175, 215]
ShowName off
Priority "5"
SourceBlock "xbsBasic/Constant"
SourceType "Xilinx Constant Block"
const "0"
arith_type "Unsigned"
n_bits "1"
bin_pt "0"
quantization "Truncate"
overflow "Wrap"
period "1"
explicit_period off
dbl_ovrd off
}
Block {
BlockType Outport
Name "coeff_addr"
Position [370, 118, 400, 132]
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType Outport
Name "data_addr"
Position [370, 43, 400, 57]
Port "2"
OutputWhenDisabled "held"
InitialOutput "[]"
}
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