Protel Design System Design Rule Check
PCB File : \Documents and Settings\Administrator\桌面\畢業(yè)設(shè)計\畢業(yè)設(shè)計\PCB1.PcbDoc
Date     : 2009-3-21
Time     : 下午 02:41:50

Processing Rule : Hole Size Constraint (Min=1mil) (Max=300mil) (All)
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=100mil) (Preferred=10mil) (All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=5mil) (All),(All)
Rule Violations :0

Processing Rule : Broken-Net Constraint ( (All) )
   Violation         Net GND   is broken into 7 sub-nets. Routed To 94.29%
     Warning - net contains unplated pads
     Subnet : JK1-26   JK1-35   JK1-10   JK1-19   JK1-40   JK1-5    JK1-44   JK1-4    JK1-3    JK1-2    
              C17-2    C19-2    C15-2    C35-2    C30-2    C16-2    C36-2    C34-2    C37-2    C18-2    C23-2    
              JMY_TIANXIAN1-3 R11-2    D2-1     C22-2    R16-2    JMY_TIANXIAN1-1 JMY_TIANXIAN1-5 C21-1    D1-1     C20-2    C25-2    
              C28-2    1-2      OCM1-20  POWER_1-3 C14-2    C12-2    C31-2    C11-2    C10-2    C33-2    L3-2     
              LED3-K   KEY1-2   C13-2    U3-4     D4-1     JP2-2    U3-3     C38-2    KEY7-2   U3-2     U3-7     
              C24-2    COM1-1   KEY2-2   C32-2    COM1-2   JP1-20   KEY3-2   POWER_2-0 KEY8-2   JP1-18   JP1-16   
              U4-1     POWER_2-1 KEY4-2   JP1-14   KEY9-2   JP1-12   U4-3     JP1-10   KEY5-2   JP1-8    KEY10-2  
              1-3      JP1-6    JP1-4    C1-2     KEY6-2   1-9      KEY11-2  KEY13-2  1-8      KEY12-2  C5-2     
              U2-1     bell1-2  OCM1-1   J1-5     C3-1     C6-2     U1-18    U1-1     S1-4     C7-2     C9-1     
              C8-2     
     Subnet : U1-13    U1-16    
     Subnet : U5-18    
     Subnet : U5-25    
     Subnet : U5-6     
     Subnet : U5-50    
     Subnet : U5-42    
Rule Violations :1

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=100mil) (Preferred=50mil) (InNet('GND'))
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=100mil) (Preferred=40mil) (InNet('4V'))
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=100mil) (Preferred=50mil) (InNet('VSSA'))
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=100mil) (Preferred=40mil) (InNet('POWER_BENQ'))
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=100mil) (Preferred=40mil) (InNet('VCC_MCU'))
Rule Violations :0

Processing Rule : Width Constraint (Min=10mil) (Max=100mil) (Preferred=30mil) (InNet('NetPOWER_1_4'))
Rule Violations :0


Violations Detected : 1
Time Elapsed        : 00:00:01