library verilog;use verilog.vl_types.all;entity sm_seq is    generic(        DLY             : integer := 1    );    port(        into            : in     vl_logic_vector(31 downto 0);        outof           : out    vl_logic_vector(31 downto 0);        rst             : in     vl_logic;        clk             : in     vl_logic;        mem             : inout  vl_logic_vector(31 downto 0);        addr            : out    vl_logic_vector(9 downto 0);        \rd_\           : out    vl_logic;        \wr_\           : out    vl_logic    );end sm_seq;