### uVision2 Project, (C) Keil Software
### Do not modify !

Target (Target 1), 0x0000 // Tools: 'MCS-51'

Group (Source Group 1)

File 1,1,<.\Series To P.c><Series To P.c>


Options 1,0,0  // Target 'Target 1'
 Device (80C51BH)
 Vendor (Intel)
 Cpu (IRAM(0-0x7F)  IROM(0-0xFFF) CLOCK(12000000))
 FlashUt ()
 StupF ()
 FlashDR ()
 DevID ()
 Rgf (REG51.H)
 Mem ()
 C ()
 A ()
 RL ()
 OH ()
 DBC_IFX ()
 DBC_CMS ()
 DBC_AMS ()
 DBC_LMS ()
 UseEnv=0
 EnvBin ()
 EnvInc ()
 EnvLib ()
 EnvReg ()
 OrgReg ()
 TgStat=16
 OutDir (.\)
 OutName (Series To P)
 GenApp=1
 GenLib=0
 GenHex=1
 Debug=1
 Browse=1
 LstDir (.\)
 HexSel=0
 MG32K=0
 TGMORE=0
 RunUsr 0 0 <>
 RunUsr 1 0 <>
 BrunUsr 0 0 <>
 BrunUsr 1 0 <>
 CrunUsr 0 0 <>
 CrunUsr 1 0 <>
 SVCSID <>
 MODEL5=0
 RTOS5=0
 ROMSZ5=2
 DHOLD5=0
 XHOLD5=0
 T51FL=80
 XT51FL=0
 CBANKS5=0
 XBANKS5=0
 RCB51 { 0,0,0,0,0,0,0,1,0 }
 RXB51 { 0,0,0,0,0,0,0,0,0 }
 OCM51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
 OCR51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
 IRO51 { 1,0,0,0,0,0,16,0,0 }
 IRA51 { 0,0,0,0,0,128,0,0,0 }
 XRA51 { 0,0,0,0,0,0,0,0,0 }
 XRA512 { 0,0,0,0,0,0,0,0,0 }
 IROM512 { 0,0,0,0,0,0,0,0,0 }
 C51FL=21630224
 C51VA=0
 C51MSC ()
 C51DEF ()
 C51UDF ()
 INCC5 ()
 AX51FL=4
 AX51MSC ()
 AX51SET ()
 AX51RST ()
 INCA5 ()
 PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
 IncBld=1
 AlwaysBuild=0
 GenAsm=0
 AsmAsm=0
 PublicsOnly=0
 StopCode=3
 CustArgs ()
 LibMods ()
 BankNo=65535
 LX51FL=292
 LX51OVL ()
 LX51MSC ()
 LX51DWN ()
 LX51LFI ()
 LX51ASN ()
 LX51RES ()
 LX51CCL ()
 LX51UCL ()
 LX51CSC ()
 LX51UCS ()
 LX51COB ()
 LX51XDB ()
 LX51PDB ()
 LX51BIB ()
 LX51DAB ()
 LX51IDB ()
 LX51PRC ()
 LX51STK ()
 LX51COS ()
 LX51XDS ()
 LX51BIS ()
 LX51DAS ()
 LX51IDS ()
  OPTDL (S8051.DLL)()(DP51.DLL)(-p51)(S8051.DLL)()(TP51.DLL)(-p51)
  OPTDBG 48126,8,()()()()()()()()()() ()()()()
 FLASH1 { 1,0,0,0,0,0,0,0,255,255,255,255,0,0,0,0,0,0,0,0 }
 FLASH2 ()
 FLASH3 ()
 FLASH4 ()
EndOpt