?? _primary.vhd
字號:
library verilog;use verilog.vl_types.all;entity RAM256X8 is port( ramdatao : in vl_logic_vector(7 downto 0); ramaddr : in vl_logic_vector(7 downto 0); ramdatai : out vl_logic_vector(7 downto 0); ramoe : in vl_logic; RAM256X8_VCC : in vl_logic; mcuclk_i_0 : in vl_logic; mcuclk : in vl_logic; RAM256X8_GND : in vl_logic; ramwe : in vl_logic );end RAM256X8;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -