library verilog;use verilog.vl_types.all;entity pll10m is    port(        pll10m_VCC      : in     vl_logic;        pll10m_GND      : in     vl_logic;        mcuclk_i        : out    vl_logic;        clk48m_c        : in     vl_logic;        mcuclk          : in     vl_logic;        mcuclk_i_0      : out    vl_logic    );end pll10m;