library verilog;use verilog.vl_types.all;entity pll10m is    port(        POWERDOWN       : in     vl_logic;        CLKA            : in     vl_logic;        LOCK            : out    vl_logic;        GLA             : out    vl_logic;        OADIVRST        : in     vl_logic    );end pll10m;