?? open source baseband bluetooth core.mht
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Subject: Open Source Baseband Bluetooth core
Date: Wed, 18 Mar 2009 10:17:55 +0530
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<HTML><HEAD><TITLE>Open Source Baseband Bluetooth core</TITLE>
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OpenSource bluetooth core, wireless baseband controller, CRC, HEC">
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<CENTER>
<H1><B>Open Source Baseband Bluetooth Core</B></H1></CENTER><I>Under=20
Construction</I>=20
<HR align=3Dcenter SIZE=3D3>
<P><FONT color=3D#000000><FONT size=3D+1>The aim of this project is to =
develop a=20
synthesizable Bluetooth cores and software stacks</FONT></FONT> =
<BR><FONT=20
color=3D#000000>If you have any comments please <A=20
href=3D"mailto:khatib@ieee.org_NOSPAM">email me</A>.</FONT>
<P>
<HR align=3Dcenter SIZE=3D3>
<H3>Introduction</H3>
<H3>Notes:</H3>This project is one of <A=20
href=3D"http://www.geocities.com/SiliconValley/Pines/6639/ip/bt/www.OpenC=
ores.org">OpenCores</A>=20
projects. You can download the latest vhdl source files from OpenCores =
<A=20
href=3D"http://www.opencores.org/cvsmodule.shtml">CVS</A> by using hte =
bluetooth=20
module name.=20
<H3>Baseband main blocks</H3>The baseband core (link controller) is =
composed of=20
the following blocks=20
<UL>
<LI>RF interface=20
<LI>LMP interface (a CPU may be)=20
<LI>Hop selection controller=20
<LI>ACL & SCO link controller=20
<LI>HEC and FEC controllers=20
<LI>Access code correlator=20
<LI>Data whitening (Scrambling)=20
<LI>Encryption=20
<LI>Authentication=20
<LI>Audio Interface=20
<LI>Clock recovery and synchronization=20
<LI>Channel Control Machine=20
<LI>RX/TX buffers and registers </LI></UL>
<HR width=3D"100%">
<CENTER>Baseband Block diagram
<P><IMG=20
src=3D"http://www.geocities.com/SiliconValley/Pines/6639/ip/bt/baseband_c=
ore.jpg"></CENTER>
<HR width=3D"100%">
<H3>Bit stream flow</H3>
<UL>
<LI><B>Header</B>: Header creation -> HEC -> scrambling =
(wightening)=20
-> FEC encoding -> combining with scrambled payload.=20
<LI><B>Payload</B>: payload insertion -> [payload CRC] -> =
[Encryption]=20
-> Scrambling (wightening)-> [FEC encoding] -> Header =
insertion=20
<LI>steps between [] depends on the packet or link type.=20
<LI>The scrambling is performed on both the header and payload and =
passed=20
serially (header then payload) to the scrambler without reinitializing =
it=20
</LI></UL>
<HR width=3D"100%">
<H3>Header Error Check (HEC):</H3>
<UL>
<LI>This block is composed of two sub-blocks, one for HEC generation =
and one=20
for HEC checking.=20
<LI>It performs error detection and correction on the packet's header. =
<LI>It holds 8 bits of CRC of the header=20
<LI>It is performed on the following 10 bits of the header <B>AM_ADDR, =
TYPE,=20
FLOW, ARQN, SEQN</B>=20
<LI>The generator poly nomial is <B>g(D)=3DD8+D7+D5+D2+D+1</B>=20
<LI>It is performed before the 1/3 FEC encoding of the header=20
<LI>It participates in ARQN & SEQN control.=20
<LI>It participates in the detection of the address because the UAP is =
used.=20
<LI>The shift register is preloaded with the slave upper address part =
(UAP) in=20
Master page response state.=20
<LI>The shift register is preloaded with the default check =
initialization=20
(DCI) which is 0x00 in the FHS packets sent in inquiry response.=20
<LI>The shift register is preloaded with the UAP of the master device. =
<LI>LSB bits of the header are entered first.=20
<LI>The LSB of UAP goes to the left-most shifter register element=20
<LI>In the checking the shift register is initialized as before and =
HEC is=20
performed on the header </LI></UL>
<CENTER>HEC Generator Top Block diagram
<P><IMG=20
src=3D"http://www.geocities.com/SiliconValley/Pines/6639/ip/bt/hec_gen_to=
p.jpg"></CENTER>
<CENTER>HEC Checker Top Block diagram
<P><IMG=20
src=3D"http://www.geocities.com/SiliconValley/Pines/6639/ip/bt/hec_chk_to=
p.jpg"></CENTER>
<CENTER>HEC register initialization
<P><IMG=20
src=3D"http://www.geocities.com/SiliconValley/Pines/6639/ip/bt/hec_init.j=
pg"></CENTER>
<CENTER>HEC core Block diagram
<P><IMG=20
src=3D"http://www.geocities.com/SiliconValley/Pines/6639/ip/bt/hec_core.j=
pg"></CENTER>
<HR width=3D"100%">
<H3>CRC:</H3>
<UL>
<LI>This block is composed of two sub-blocks, one for CRC generation =
and one=20
for CRC checking.=20
<LI>It performs error detection and correction on the packet's =
payload.=20
<LI>It holds 16 bits of CRC of the payload=20
<LI>The generator poly nomial is (CRC-CCITT) =
<B>g(D)=3DD16+D12+D5+1</B>=20
<LI>It participates in ARQN & SEQN control.=20
<LI>It is not performed on all types of packets.=20
<LI>CRC is performed on the following ACL links packets=20
<B>DM1,DH1,DM1,DH3,DM5,DH5</B>=20
<LI>CRC is performed on the data part of the <B>DV</B> SCO link =
packets only=20
<LI>CRC is performed on <B>FHS</B> packets=20
<LI>CRC is done before any possible FEC encoding=20
<LI>It participates in the detection of the address because the UAP is =
used.=20
<LI>The shift register is preloaded with the slave upper address part =
(UAP) in=20
Master page response state FHS packet.=20
<LI>The shift register is preloaded with the default check =
initialization=20
(DCI) which is 0x00 in the FHS packets sent in inquiry response.=20
<LI>The shift register is preloaded with the UAP of the master device. =
<LI>Since the UAP and DCI are 8 bit values, they are loaded into the 8 =
least=20
significant (left-most) and other bits are set to zero=20
<LI>The CRC code is appended to the information.=20
<LI>In the checking the shift register is initialized as before and =
CRC is=20
performed on the header=20
<LI>LSB bits of the data are entered first.=20
<LI>The data bits are shifted into the LFSR and when they are finished =
the=20
Switsh (S shown in the figure) passes zeros to the LFSR.=20
<LI>The CRC and HEC blocks are very similar except that HEC must be =
done in=20
all packets and it is 8 bits while CRC is done on some packets and is =
16-bit=20
</LI></UL>
<CENTER>crc Generator Top Block diagram
<P><IMG=20
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