Release 6.3i - xst G.35Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.81 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.81 s | Elapsed : 0.00 / 1.00 s --> Reading design: bcd_7seg.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : bcd_7seg.prjInput Format                       : mixedIgnore Synthesis Constraint File   : NOVerilog Include Directory          : ---- Target ParametersOutput File Name                   : bcd_7segOutput Format                      : NGCTarget Device                      : xc3s50-5-pq208---- Source OptionsTop Module Name                    : bcd_7segAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESMux Style                          : AutoDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : autoAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 500Add Generic Clock Buffer(BUFG)     : 8Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : ONLYWrite Timing Constraints           : NOHierarchy Separator                : _Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : bcd_7seg.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESOptimize Instantiated Primitives   : NO==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd in Library work.Architecture behavioral of Entity bcd_7seg is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <bcd_7seg> (Architecture <behavioral>).Entity <bcd_7seg> analyzed. Unit <bcd_7seg> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <bcd_7seg>.    Related source file is G:/vijay_FPGA_LAB/bcd_7seg/bcd_7seg.vhd.    Found 16x8-bit ROM for signal <dis_out>.    Summary:	inferred   1 ROM(s).Unit <bcd_7seg> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs                             : 1 16x8-bit ROM                      : 1==================================================================================================================================================*                         Low Level Synthesis                           *==================================================================================================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : bcd_7seg.ngrKeep Hierarchy                     : NODesign Statistics# IOs                              : 16Cell Usage :# BELS                             : 2#      GND                         : 1#      VCC                         : 1=========================================================================CPU : 8.81 / 10.38 s | Elapsed : 9.00 / 10.00 s --> Total memory usage is 51448 kilobytes