/* cacheSh7700Lib.c - Hitachi SH7700 cache management library *//* Copyright 1996-2001 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01p,23nov01,hk  removed checking vmLibInfo.vmLibInstalled in cacheSh7700DmaFree		and cacheSh7700P2DmaFree for INCLUDE_MMU_BASIC (SPR 71807).01p,24oct01,zl  fixes for doc builds.01o,27feb01,hk  add Hitachi to library description.01n,07dec00,hk  set cacheMmuAvailable to T/F depending on data cache mode.01m,21nov00,hk  changed to ignore instMode in cacheSh7700LibInit(). changed		cacheLib.invalidateRtn to cacheSh7700Clear() in copyback mode.		made cacheSh7700Disable() NMI-safe.01l,20aug00,hk  moved critical operations to cacheSh7700ALib. made cache tag		operations more precise. improved cacheSh7700P2DmaMalloc().		added cache dump tools.01k,06feb98,jmc renamed CACHE_WRITEBACK_P1 to CACHE_COPYBACK_P1.01j,30jan98,jmc revised cacheSh7700LibInit() to set CCR bit CCR_WRITE_BACK_P1		if mode is CACHE_WRITEBACK_P1, write-back cache for P1 region,		SH7709 only.01i,12jan98,hk  fixed docs for cacheSh7700LibInit(), changed two to next.01h,22mar97,hk  reviewed documentation.01g,16feb97,hk  added support for SH7702. changed CCR_RAM_MODE to CCR_2WAY_MODE.01f,19jan97,hk  disabled & invalidated cache at a time in cacheSh7700LibInit().                removed address range check from cacheArchInvalidate() and                cacheArchClear(). supported CACHE_2WAY_MODE in cacheArchClear().                Deleted intLock() in cacheArchClear(). specified DATA_CACHE in                cacheArchDmaMallocP2 instead of 0.01e,18jan97,hk  made cacheArchXXX local, and registered P2 address to cacheLib                structure. added CACHE_COPYBACK and CACHE_DMA_BYPASS_P[013].                simplified cacheArchEnable(). added cacheArchInvalidate().                added cache entry purge code. made cacheArchDmaMalloc/Free()                to use mmu and renamed non-mmu version as xxxP2(). cacheTest().01d,30dec96,hk  made cacheLib.textUpdateRtn NULL for copyback support. updated                address space macro names for cacheShLib.h-01n.01c,25sep96,hk  cacheArchClear() clears whole cache.(temporal)01b,05sep96,hk  take no action to enable/disable INSTRUCTION_CACHE. substituted		macros to magic numbers in cacheArchDmaMalloc/cacheArchDmaFree.01a,23aug96,hk  derived from cacheSh7604Lib.c-01q.*//*DESCRIPTIONThis library contains architecture-specific cache library functions forthe Hitachi SH7700 architecture.  There is a 8-Kbyte (2-Kbyte for SH7702)mixed instruction and data cache that operates in write-through orwrite-back (copyback) mode.  The 8-Kbyte cache can be divided into4-Kbyte cache and 4-Kbyte memory.  Cache line size is fixed at 16 bytes,and the cache address array holds physical addresses as cache tags.Cache entries may be "flushed" by accesses to the address array in privilegedmode.  There is a write-back buffer which can hold one line of cache entry,and the completion of write-back cycle is assured by accessing to any cachethrough region.For general information about caching, see the manual entry for cacheLib.INCLUDE FILES: cacheLib.hSEE ALSO: cacheLib*/#include "vxWorks.h"#include "errnoLib.h"#include "cacheLib.h"#include "intLib.h"			/* for intLock()/intUnlock() */#include "memLib.h"			/* for memalign() */#include "stdlib.h"			/* for malloc()/free() */#include "string.h"			/* for bzero() */#include "private/memPartLibP.h"	/* for BLOCK_TO_HDR() */#include "private/vmLibP.h"#include "private/funcBindP.h"		/* for _func_valloc *//* imports */IMPORT void cacheSh7700CCRSetOp (UINT32 ccr);IMPORT UINT32 cacheSh7700CCRGet (void);IMPORT STATUS cacheSh7700OnOp (BOOL on);IMPORT void cacheSh7700CFlushOp (void);IMPORT void cacheSh7700AFlushOp (UINT32 from, UINT32 to);IMPORT void cacheSh7700MFlushOp (UINT32 *pt, int ix, UINT32 from, UINT32 to);/* local definitions */#define CAC_RAM_ADRS		0x7f000000#define CAC_RAM_SIZE		4096#define CAC_ADRS_ARRAY		0xf0000000#define CAC_DATA_ARRAY		0xf1000000#define CAC_DATA_SIZE		8192#define CAC_LINE_SIZE		16/* SH7700 Cache Control Register bit define */#define CCR_2WAY_MODE		0x00000020	/* 4KB 2-way cache + 4KB RAM */#define CCR_1WAY_MODE		0x00000010	/* 2KB direct mapped cache */#define CCR_CACHE_FLUSH		0x00000008	/* no write back */#define CCR_WRITE_BACK_P1	0x00000004	/* set P1 to write-back */#define CCR_WRITE_THRU		0x00000002#define CCR_CACHE_ENABLE	0x00000001/* forward declarations */LOCAL STATUS cacheSh7700Enable (CACHE_TYPE cache);LOCAL STATUS cacheSh7700Disable (CACHE_TYPE cache);LOCAL STATUS cacheSh7700Clear (CACHE_TYPE cache, void *from, size_t bytes);LOCAL STATUS cacheSh7700Invalidate (CACHE_TYPE cache, void *from, size_t bytes);LOCAL void * cacheSh7700DmaMalloc (size_t bytes);LOCAL STATUS cacheSh7700DmaFree (void * pBuf);LOCAL void * cacheSh7700P2DmaMalloc (size_t bytes);LOCAL STATUS cacheSh7700P2DmaFree (void * pBuf);/* local function pointers to relocate cacheSh7700ALib entries */LOCAL VOIDFUNCPTR cacheSh7700CCRSet = (VOIDFUNCPTR)0x1234;LOCAL FUNCPTR     cacheSh7700On     =     (FUNCPTR)0x1234;LOCAL VOIDFUNCPTR cacheSh7700CFlush = (VOIDFUNCPTR)0x1234;LOCAL VOIDFUNCPTR cacheSh7700AFlush = (VOIDFUNCPTR)0x1234;LOCAL VOIDFUNCPTR cacheSh7700MFlush = (VOIDFUNCPTR)0x1234;/******************************************************************************** cacheSh7700LibInit - initialize the SH7700 cache library* * This routine initializes the cache library for the Hitachi SH7700 processor.* It initializes the function pointers and configures the caches to the* specified cache modes.  Modes should be set before caching is enabled.* If two complementary flags are set (enable/disable), no action is taken* for any of the input flags.** The following caching modes are available for the SH7700 processor:** .TS* tab(|);* l l l l.* | SH7700:| CACHE_WRITETHROUGH  | (cache for instruction and data)* |        | CACHE_COPYBACK      | (cache for instruction and data)* |        | CACHE_COPYBACK_P1   | (copy-back cache for P1, SH7709 only)* |        | CACHE_2WAY_MODE     | (4KB 2-way cache + 4KB RAM)* |        | CACHE_1WAY_MODE     | (2KB direct mapped cache, SH7702 only)* |        | CACHE_DMA_BYPASS_P0 | (allocate DMA buffer to P2, free it to P0)* |        | CACHE_DMA_BYPASS_P1 | (allocate DMA buffer to P2, free it to P1)* |        | CACHE_DMA_BYPASS_P3 | (allocate DMA buffer to P2, free it to P3)* .TE** The CACHE_DMA_BYPASS_Px modes allow to allocate "cache-safe" buffers without* MMU.  If none of CACHE_DMA_BYPASS_Px modes is specified, cacheDmaMalloc()* returns a cache-safe buffer on logical space, which is created by the MMU.* If CACHE_DMA_BYPASS_P0 is selected, cacheDmaMalloc() returns a cache-safe* buffer on P2 space, and cacheDmaFree() releases the buffer to P0 space.* Namely, if the system memory partition is located on P0, cache-safe buffers* can be allocated and freed without MMU, by selecting CACHE_DMA_BYPASS_P0.* * RETURNS: OK, or ERROR.*/STATUS cacheSh7700LibInit    (    CACHE_MODE	instMode,	/* instruction cache mode (ignored) */    CACHE_MODE	dataMode	/* data cache mode */    )    {    /* setup function pointers for cache library (declared in funcBind.c) */    cacheLib.enableRtn          = cacheSh7700Enable;    cacheLib.disableRtn         = cacheSh7700Disable;    cacheLib.lockRtn            = NULL;    cacheLib.unlockRtn          = NULL;    /* Flush and invalidate are the same in COPYBACK mode.  Setting the flush     * bit in the CCR doesn't do a write-back, so call cacheSh7700Clear if     * using COPYBACK (write-back) mode.     */    if (dataMode & (CACHE_COPYBACK | CACHE_COPYBACK_P1))	{	cacheLib.flushRtn	= cacheSh7700Clear;	cacheLib.invalidateRtn	= cacheSh7700Clear;	}    else	{	cacheLib.flushRtn	= NULL;	cacheLib.invalidateRtn	= cacheSh7700Invalidate;	}    cacheLib.clearRtn           = cacheSh7700Clear;    cacheLib.textUpdateRtn      = NULL;		/* inst/data mixed cache */    cacheLib.pipeFlushRtn       = NULL;    /* setup P2 function pointers for cache sensitive operations */    cacheSh7700CCRSet		= (VOIDFUNCPTR)(((UINT32)cacheSh7700CCRSetOp				& SH7700_PHYS_MASK) | SH7700_P2_BASE);    cacheSh7700On		= (FUNCPTR)(((UINT32)cacheSh7700OnOp				& SH7700_PHYS_MASK) | SH7700_P2_BASE);    cacheSh7700CFlush		= (VOIDFUNCPTR)(((UINT32)cacheSh7700CFlushOp				& SH7700_PHYS_MASK) | SH7700_P2_BASE);    cacheSh7700AFlush		= (VOIDFUNCPTR)(((UINT32)cacheSh7700AFlushOp				& SH7700_PHYS_MASK) | SH7700_P2_BASE);    cacheSh7700MFlush		= (VOIDFUNCPTR)(((UINT32)cacheSh7700MFlushOp				& SH7700_PHYS_MASK) | SH7700_P2_BASE);    /* select cache-safe malloc/free routines for DMA buffer */    if (dataMode &        (CACHE_DMA_BYPASS_P0 | CACHE_DMA_BYPASS_P1 | CACHE_DMA_BYPASS_P3))	{	cacheLib.dmaMallocRtn   = (FUNCPTR)cacheSh7700P2DmaMalloc;	cacheLib.dmaFreeRtn     = cacheSh7700P2DmaFree;	cacheMmuAvailable	= TRUE;		/* for cacheFuncsSet() */	}    else	{	cacheLib.dmaMallocRtn   = (FUNCPTR)cacheSh7700DmaMalloc;	cacheLib.dmaFreeRtn     = cacheSh7700DmaFree;	cacheMmuAvailable	= FALSE;	/* needs MMU support for cache						   safe allocation */	}    cacheLib.dmaVirtToPhysRtn	= NULL;    cacheLib.dmaPhysToVirtRtn	= NULL;    /* check for parameter errors */    if ((dataMode & ~(CACHE_WRITETHROUGH | CACHE_COPYBACK | CACHE_2WAY_MODE |             CACHE_DMA_BYPASS_P0 | CACHE_DMA_BYPASS_P1 | CACHE_DMA_BYPASS_P3 |             CACHE_1WAY_MODE | CACHE_COPYBACK_P1)) ||	((dataMode & CACHE_WRITETHROUGH)  && (dataMode & CACHE_COPYBACK))     ||	((dataMode & CACHE_DMA_BYPASS_P0) && (dataMode & CACHE_DMA_BYPASS_P1))||	((dataMode & CACHE_DMA_BYPASS_P1) && (dataMode & CACHE_DMA_BYPASS_P3))||	((dataMode & CACHE_DMA_BYPASS_P3) && (dataMode & CACHE_DMA_BYPASS_P0))||	((dataMode & CACHE_2WAY_MODE)     && (dataMode & CACHE_1WAY_MODE)))	{	errnoSet (S_cacheLib_INVALID_CACHE);	return ERROR;	}    /* initialize cache modes (declared in cacheLib.c) */    cacheDataMode	= dataMode;    cacheDataEnabled	= FALSE;    /* disable cache safely */    cacheLib.disableRtn (DATA_CACHE);    /* initialize CCR, clear on-chip RAM if available */	{	UINT32 ccr = 0;	if (dataMode & CACHE_WRITETHROUGH) ccr |= CCR_WRITE_THRU;	if (dataMode & CACHE_2WAY_MODE)    ccr |= CCR_2WAY_MODE;	if (dataMode & CACHE_1WAY_MODE)    ccr |= CCR_1WAY_MODE;	if (dataMode & CACHE_COPYBACK_P1)  ccr |= CCR_WRITE_BACK_P1;	cacheSh7700CCRSet (ccr);	if (cacheSh7700CCRGet () & CCR_2WAY_MODE)	    bzero ((char *)CAC_RAM_ADRS, CAC_RAM_SIZE);	/* clear on-chip RAM */	}    return OK;    }/******************************************************************************** cacheSh7700Enable - enable a SH7700 cache** This routine invalidates and enables the specified SH7700 cache.*              ^^^^^^^^^^^     ^^^^^^^* RETURNS: OK, or ERROR if the specified cache type was invalid.** NOMANUAL*/LOCAL STATUS cacheSh7700Enable    (    CACHE_TYPE cache    )    {    STATUS status;    switch (cache)	{	case DATA_CACHE:	    if ((status = cacheSh7700On (TRUE)) == OK)		{		cacheDataEnabled = TRUE;		cacheFuncsSet ();	/* set cache function pointers */		}	    break;	default:	    errno = S_cacheLib_INVALID_CACHE;	case INSTRUCTION_CACHE:	    status = ERROR;	}    return status;    }/******************************************************************************** cacheSh7700Disable - disable a SH7700 cache** This routine flushes and disables the specified SH7700 cache.*              ^^^^^^^     ^^^^^^^^* RETURNS: OK, or ERROR if the specified cache type was invalid.** NOMANUAL*/LOCAL STATUS cacheSh7700Disable    (    CACHE_TYPE cache    )    {    STATUS status;    switch (cache) 	{	case DATA_CACHE:	    if ((status = cacheSh7700On (FALSE)) == OK)	/* flush and disable */		{		cacheDataEnabled = FALSE;		cacheFuncsSet ();	/* clear cache function pointers */		}	    break;	default:	    errno = S_cacheLib_INVALID_CACHE;	case INSTRUCTION_CACHE:	    status = ERROR;	}    return status;    }/******************************************************************************** cacheSh7700Invalidate - invalidate all or some entries from a SH7700 cache** This routine invalidates all or some entries of the SH7700 cache.** RETURNS: OK, or ERROR if the cache type is invalid or the cache control* is not supported.** NOMANUAL*/LOCAL STATUS cacheSh7700Invalidate    (    CACHE_TYPE cache,    void *     from,    size_t     bytes    )    {    if (bytes == ENTIRE_CACHE)	{	UINT32 ccr = cacheSh7700CCRGet ();	if ((ccr & (CCR_WRITE_BACK_P1 | CCR_WRITE_THRU)) == CCR_WRITE_THRU)	    {	    cacheSh7700CFlush ();	    return OK;	    }	}    return cacheSh7700Clear (cache, from, bytes);    }/******************************************************************************** cacheSh7700Clear - clear all or some entries from a SH7700 cache** This routine flushes and invalidates all or some entries of the specified* SH7700 cache.** RETURNS: OK, or ERROR if the cache type is invalid or the cache control* is not supported.** NOMANUAL*/LOCAL STATUS cacheSh7700Clear    (    CACHE_TYPE cache,    void *     from,		/* address to clear */    size_t     bytes    )    {