/* excALib.s - exception handling SH assembly language routines *//* Copyright 1994-2001 Wind River Systems, Inc. */	.data	.global	_copyright_wind_river	.long	_copyright_wind_river/*modification history--------------------03e,10dec01,zl   added leading underscore to areWeNested.03d,08nov01,hk   courtesies of Hans-Erik and Hitachi-Japan, added mmuPciStub.03c,03nov01,zl   made excNonTrapa local.03b,10sep01,zl   FPSCR exception info for _WRS_HW_FP_SUPPORT only.03a,03sep00,hk   change excUnblock to preserve SR.DSP.		 change small constants to use .word storage.		 lock interrupts in excDispatch before using bank-1 registers.		 use intBlockSR (ex-0x70000000) to block exceptions.		 merge intLockIntSR to intLockTaskSR.		 put together .text directives.		 add .size directive to global constants.02z,21aug00,hk   merge SH7729 to SH7700. merge SH7410 and SH7040 to SH7600.02y,20jun00,hk   fixed excStub/excIntStub/excBsrTbl for SH7600.02x,20apr00,hk   changed sysBErrVecNum to excBErrVecNum. changed text alignment                 to _ALIGN_COPY_TEXT, for stubs to be copied before use.02w,10apr00,hk   got rid of .ptext section: modified excBErrStub as a VBR-                 relative code in P1/P2. also changed intPrioTable and                 areWeNested to VBR-relative data.  changed inter-stub                 branches to jumps.02v,28mar00,hk   added .type directive to function names and tables.02u,17mar00,zl   made use of alignment macro _ALIGN_TEXT02t,16jun99,zl   added instrunction to save EXPEVT in _excStub02s,08jun99,zl   added .ptext attribute "ax"02r,02mar99,hk   merged mmuStub.02n,28may98,jmc  added support for SH-DSP and SH3-DSP.02o,04nov98,hk   changed excBErrStub/excIntStub for new intStub design(SH7700).02n,12may98,hk   added SH7718(SH3e) on-chip FPU exception support.02q,08oct98,hk   improved mmuStub for SH7750. unified coding in excStub.02p,16sep98,hk   code review: simplified CPU conditionals. unified SH7750_VEC_                 TABLE_OFFSET to SH7700_VEC_TABLE_OFFSET.02o,16sep98,st   deleted dummy code in mmuStub().02n,16jul98,st   added SH7750 support.02m,25nov97,hk   changed to use sequential interrupt number for SH7700.02l,19jun97,hk   moved in mmuStub from mmuSh7700ALib.s.02k,27apr97,hk   changed SH704X to SH7040.02j,03mar97,hk   moved excTlbStub to relax code layout. merged excUnknown                 to excSetDefault. reviewed comment.02i,23feb97,hk   added sanity check for EXPEVT value.02h,17feb97,hk   pushed EXPEVT on stack. deleted unused INTEVT def. fixed                 TRA/TEA push logic for address error exception w/mmu.                 minimized bank1 register usage. made excNonTrapa global for                 branching from mmuStub. simplified SR.BL unblocking code.02g,12feb97,hk   adjusted excBErrStub/excIntStub for pushed INTEVT on stack.02f,09feb97,hk   fixed _excStub for SH7700 to handle protection exceptions.02e,18jan97,hk   saved TRA/TEA on top of stack.02d,03jan97,hk   added excTLBfixed.02c,25dec96,hk   fixed comment for excStub.02b,21dec96,hk   moved SH3 code to .ptext. excluded _excBErrStub from                 _excStubSize. renamed AAreWeNested as AreWeNested.02a,16dec96,hk   added wt's TLB invalid exception support code to excStub.01z,13dec96,hk   fixed excIntStub for SH[127m] to pop errno in r1.01y,09dec96,wt   changed excStub not to use stack while blocked, and kept	   +hk   volatiles in bank regs. overhauled excBErrStub/excIntStub.01x,29sep96,hk   added excBackToTaskContext to handle exception in task context.		 fixed r0 on stack for non-nested case. changed blocking sr to		 0x50000000 before rte. special thanks to wt for this to fix.01w,26sep96,hk   changed cmp/eq in excUnblock to tst, to use r2 instead of r0.01v,17sep96,hk   fixed r5 in excStub to point ESF before calling excExcHandle.		 added bypass for BL unblocking. made regular exception to fetch		 its handler from virtual vector table, but forced bus error to		 call excExcHandle. noted that rte code in excStub is not used.		 renamed excBErrExc to _excBErrStub, and made it to be directly		 called from _intStub. added documentation to _excBErrStub.01u,02sep96,hk   changed exception stack design and excBErrExc for SH7700.01t,22aug96,hk   deleted bank registers from REG_SET, trying bus err exception.01s,19aug96,hk   changed code layout. changed SH7700 excIntStub for new intStub.01r,14aug96,hk   deleted bank switch in excStub. intPrioTable covers exception.01q,13aug96,hk   fixed excIntStub for SH7700 to do rts.01p,13aug96,hk   added excIntStub for SH7700.01o,09aug96,hk   added 'trapa' handling code for SH7700. currently overlaying		 the trap vector table to exception/interrupt virtual vectbl.01n,08aug96,hk   deleted #include "excLib.h". changed EXPEVT to 8bit immediate.		 also added TRA def. changed SH7700_VEC_OFFSET according to		 new ivSh.h (01t).01m,08aug96,hk   added notes on excStub for SH7700.01l,04aug96,hk   changed code layout. added bank control for SH7700.01k,29jul96,hk   changed to use 'mova', added DEBUG_LOCAL_SYMBOLS option.01j,26jul96,ja   call excHandler via ExcVecTbl.01i,11jul96,ja   added excStubSize: for SH7700.01h,13jun96,hk   added excStub: for SH7700.01g,08apr96,hk   moved ExcBsrTblBErr/ExcBsrTbl to restore 256 BSR table.01e,28mar96,ja   resized BSR table 256 ->166: fix pcrel too far.01f,18dec95,hk   added support for SH704X.01e,19may95,hk   worked around 'mova' alignment problem.01d,06apr95,hk   deleted excBsrTbl entries over 128.01c,27mar95,hk   added bus error support. copyright 1995.01b,05dec94,hk   modified for pc/sr swapping in REG_SET.01a,27oct94,hk   taken from 68k 02c.*//*DESCRIPTIONThis module contains the assembly language exception handling stub.It is connected directly to the SH exception vectors.It sets up an appropriate environment and then calls a routinein excLib(1).SEE ALSO: excLib(1)*/#define _ASMLANGUAGE#include "vxWorks.h"#include "iv.h"#include "asm.h"#if	(CPU==SH7750 || CPU==SH7700)#if	(SH7700_TLB_STUB_OFFSET > 0x7fff)#error	SH7700_TLB_STUB_OFFSET > 0x7fff, check ivSh.h#endif#if	(SH7700_VEC_TABLE_OFFSET > 0x7fff)#error	SH7700_VEC_TABLE_OFFSET > 0x7fff, check ivSh.h#endif#if	(SH7700_INT_PRIO_TABLE_OFFSET > 0x7fff)#error	SH7700_INT_PRIO_TABLE_OFFSET > 0x7fff, check ivSh.h#endif#if	(SH7700_EXC_STUB_OFFSET > 0x7fff)#error	SH7700_EXC_STUB_OFFSET > 0x7fff, check ivSh.h#endif#endif	/* CPU==SH7750 || CPU==SH7700 */	.text	/* globals */	.global	_excStub	.global	_excIntStub#if	(CPU==SH7750 || CPU==SH7700)	.global	_excStubSize	.global	_excBErrStub	.global	_excBErrStubSize	.global	_mmuStub	.global	_mmuStubSize#elif	(CPU==SH7600 || CPU==SH7000)	.global	_excBsrTbl	.global	_excBsrTblBErr#endif	/*CPU==SH7600 || CPU==SH7000*/#if	(CPU==SH7750)	/* globals for SH7751 virtual PCI space extension */	.global	_mmuPciStub	.global	_mmuPciStubSize	.global	_mmuPciStubParams	.global	_mmuPciIoStub	.global	_mmuPciIoStubSize	.global	_mmuPciIoStubParams	.global	_mmuStubProper	.global	_mmuStubProperSize#endif	/* CPU==SH7750 */	/* imports */	.extern	_excBErrVecNum		/* excArchLib */	.extern	_excExcHandle		/* excArchLib */	.extern	_excIntHandle		/* excArchLib */	.extern	_intCnt			/* intLib */	.extern	_errno			/* errnoLib */	.extern	_intExit		/* windALib */	.extern	_intLockTaskSR		/* intArchLib */#if	(CPU==SH7750 || CPU==SH7700)	.extern	_intBlockSR		/* intArchLib */#elif	(CPU==SH7600 || CPU==SH7000)	.extern	_vxIntStackBase		/* kernelLib */	.extern	_areWeNested		/* windALib */#endif	/*CPU==SH7600 || CPU==SH7000*/	/* local definitions */#if	(CPU==SH7750)#define TRA	0x20		/* 0xff000020: TRApa exception register */#define EXPEVT	0x24		/* 0xff000024: Exception Event	      */#define TEA	0x0c		/* 0xff00000c: TLB Exception Address    */#elif	(CPU==SH7700)#define TRA	0xd0		/* 0xffffffd0: TRApa exception register */#define EXPEVT	0xd4		/* 0xffffffd4: EXception EVenT register */#define TEA	0xfc		/* 0xfffffffc: TLB Exception Address    */#endif	/*CPU==SH7700*/#if (CPU==SH7750 || CPU==SH7700)/******************************************************************************** excStub - exception handler (SH7750/SH7700)** This is the exception dispatcher that is pointed by the SH77XX exception* vector.  These instructions are copied to (vbr + 0x100), the SH77XX* exception vector by the startup routine excVecInit().  In this routine* we take care of saving state, and jumping to the appropriate routines.* On exit from handling we also return here to restore state properly.* * This routine is not callable!!  This routine does not include save and* restore of floating point state.** NOMANUAL**		|_____________|     +60       __________*		|TRA/TEA/FPSCR| 96  +56  +12         ^*		|   EXPEVT    | 92  +52  +8   _____  | ESFSH*		|     ssr     | 88  +48  +4	^    |*	r5 --->	|     spc     | 84  +44  +0	| ___v__*		|     r15     | 80  +40		|*		|     r14     | 76  +36		|*		|     r13     | 72  +32		|*		|     r12     | 68  +28		|*		|     r11     | 64  +24		|*		|     r10     | 60  +20		|*		|     r9      | 56  +16		|*		|     r8      | 52  +12		|*		|    macl     | 48  +8		|*		|    mach     | 44  +4     REG_SET*		|     r7      | 40  +0		|*		|     r6      | 36		|*		|     r5      | 32		|*		|     r4      | 28		|*		|     r3      | 24		|		+--------+*		|     r2      | 20		|	     r6 |REG_SET*|*		|     r1      | 16		|		+--------+*		|     r0      | 12		|	     r5 | ESFSH *|*		|     pr      |  8		|		+--------+*		|     gbr     |  4		|	     r4 |  INUM  |*       r6 --->	|____ vbr ____|  0    __________v__		+--------+*               |             |*/	.align	_ALIGN_COPY_TEXT	.type	_excStub,@function_excStub:			/* MD=1, RB=1, BL=1, IM=? */#if	(CPU==SH7750)	mov.l	EFF000000,r1	mov.l	@(EXPEVT,r1),r0#else	mov	#EXPEVT,r1	mov.l	@r1,r0#endif	cmp/eq	#0x40,r0	/* 0x40: TLB invalid (read) */	bt	excTlbStub	cmp/eq	#0x60,r0	/* 0x60: TLB invalid (write) */	bt	excTlbStub#ifdef	_WRS_HW_FP_SUPPORT	mov.w	EvtFpu,r1	cmp/eq	r1,r0		/* 0x120: FPU exception */	bt.s	excFpuStub;	mov	r0,r5		/* r5_bank1 = EXPEVT */#endif	mov.w	EvtTrapa,r1	cmp/eq	r1,r0		/* 0x160: Unconditional Trap */	bf.s	excNonTrapa	mov	r0,r5		/* r5_bank1 = EXPEVT */#if	(CPU==SH7750)	mov.l	EFF000000,r1	bra	excInfoGet;	add	#TRA,r1#else	bra	excInfoGet;	mov	#TRA,r1#endifexcTlbStub:	mov.w	MMU_STUB_OFFSET,r1;	stc	vbr,r0	add	r1,r0	jmp	@r0;		/* ---> mmuStub: at (vbr + 0x400) */	nop#ifdef	_WRS_HW_FP_SUPPORTexcFpuStub:	bra	excUnblock;	sts	fpscr,r4#endifexcNonTrapa:			/* <--- mmuStubErr:  */#if	(CPU==SH7750)	mov.l	EFF000000,r1;	add	#TEA,r1#else	mov	#TEA,r1#endifexcInfoGet:			/* r5_bank1 = EXPEVT */	mov.l	@r1,r4		/* r4_bank1 = TRA or TEA */excUnblock:			/* r4_bank1 = TRA or TEA or FPSCR */	stc	ssr,r6		/* r6_bank1 = ssr    */	stc	spc,r7		/* r7_bank1 = spc    */	mov.l	XCFFFFFFF,r1	/* r1: 0xcfffffff */	stc	sr,r0		/* r0: 0x7___?_?_ */	or	#0xf0,r0	/* r0: 0x7___?_f_ */	and	r1,r0		/* r0: 0x4___?_f_ */	ldc	r0,sr		/* UNBLOCK EXCEPTION (enable mmuStub), RB=0 */	stc.l	r4_bank,@-sp				/* save TRA/TEA/FPSCR */	stc.l	r5_bank,@-sp				/* save EXPEVT    */	stc.l	r6_bank,@-sp;	stc.l	r7_bank,@-sp	/* save ssr/spc   */	add	#-4,sp;		mov.l	r14, @-sp	/* save     r14   */	mov.l	r13, @-sp;	mov.l	r12, @-sp	/* save r13/r12   */	mov.l	r11, @-sp;	mov.l	r10, @-sp	/* save r11/r10   */	mov.l	r9,  @-sp;	mov.l	r8,  @-sp	/* save r9/r8     */	sts.l	macl,@-sp;	sts.l	mach,@-sp	/* save macl/mach */	mov.l	r7,  @-sp				/* save r7        */	mov	sp,  r7	add	#60, r7	mov.l	r7,  @(40,sp)				/* save as r15  */				mov.l	r6,  @-sp	/* save    r6   */	mov.l	r5,  @-sp;	mov.l	r4,  @-sp	/* save r5/r4   */	mov.l	r3,  @-sp;	mov.l	r2,  @-sp	/* save r3/r2   */	mov.l	r1,  @-sp;	mov.l	r0,  @-sp	/* save r1/r0   */	sts.l	pr,  @-sp				/* save pr      */	stc.l	gbr, @-sp;	stc.l	vbr, @-sp	/* save gbr/vbr */	mov	sp,  r5	add	#84, r5		/* r5: --> ESF */	mov.l	@(8,r5),r4	/* r4: EXPEVT 0x080, 0x0a0, ... 0x1d0 */	mov	r4,r0		/* do sanity check for EXPEVT code */	tst	#0x1f,r0	bf	excSetDefault	/*(EXPEVT & 0x1f) != 0, this should not happen*/	mov	#0x40,r1	cmp/hs	r1,r0	bf	excSetDefault	/* EXPEVT < 0x40, this should not happen */	shll2	r1	shll2	r1	cmp/hs	r1,r0	bt	excSetDefault	/* EXPEVT >= 0x400, this should not happen */	mov.w	IntPrioTableOffset,r1	stc	vbr,r0	add	r1,r0	mov	r4,r3	mov	#-3,r1	shld	r1,r3		/* r3: 0x0, 0x4 */	mov.l	@(r0,r3),r2	/* fetch sr from intPrioTable[] */	mov.w	EvtTrapa,r1	/* If this is a trap exception, read */	cmp/eq	r4,r1		/* TRA value and map it over the sh3 */