** This is an optional TLB mishit exception handler which enables to extend* the PCI window size of SH7751. The original PCI window size is 16MB for* memory space and 256KB for IO space, and an effective PCI bus address is* specified as a sum of a window offset and a window base address in PCIMBR/* PCIIOBR register.  The idea is to map every 16MB/256KB page in a user* defined virtual PCI space to the same physical PCI window memory, using* the TLB mishit exceptions to update the corresponding base register when* the effective address of the exception lies within the virtual PCI space.** The problem with this scheme is that you can't guarantee that you will always* get a TLB mishit exception when you switch between the virtual PCI pages,* because the previous virtual-to-physical mappings are cached in the UTLB.* To solve this problem, we use the URC field in the MMUCR register to load* a PCI mapping to an unique UTLB entry: #63 for PCI memory mapping, and #62* for PCI I/O mapping.  The URB field in the MMUCR register is initialized* by excPciMapInit() to reserve these UTLB entries.  This means that there will* ever be only one mapping in the UTLB for PCI memory space and another one* mapping for PCI I/O space, so that you will always get an exception when* you go beyond a PCI page boundary.  The used page size differs on each space:* 1MB for PCI memory space, 64KB for PCI IO space, and 4KB for other regular* non-PCI space.** This handler is composed of three parts: mmuPciStub, mmuPciIoStub, and* mmuStubProper.  The initialization is managed by excPciMapInit(), only* the necessary handler parts are pasted in (VBR+0x400) and some immediate* constants are modified to describe the virtual PCI space parameters.* As mentioned above, the excPciMapInit() also tells mmuSh7750LibInit() to* reserve a few UTLB entries.  The mmuPciStub part takes care of PCI memory* space mapping, and the mmuPciIoStub part takes care of PCI IO space mapping.* The regular TLB refill part (mmuStubProper) picks up a new PTEL value from* a page table, but other two parts (mmuPciStub/mmuPciIoStub) assemble a new* PTEL value from a requested virtual address information in PTEH.  Therefore* these virtual PCI spaces do not need a page table which would affect on* system memory usage.** NOMANUAL*/	.align	_ALIGN_TEXT	.type	_mmuPciStub,@function_mmuPciStub:				/* MD=1, RB=1, BL=1, IM=? */	mov.l	MP_XFF000000,r3;	mov.l	MP_PCI_VMEM_LOW,r0;	/* Lower PCI memory space boundary */	mov.l	@(TEA,r3),r1;	mov.l	MP_PCI_VMEM_HIGH,r2;	/* Upper PCI memory space boundary */	cmp/hi	r1,r0	bt	mmuPciStubEnd	cmp/hs	r2,r1	bt	mmuPciStubEnd	mov.l	MP_PCI_PMEM_BASE,r0;	and	r3,r1			/* r1: TEA & 0xff000000 */	mov.l	MP_PCIMBR,r2;	add	r0,r1	mov.l	@r2,r0;	and	#1,r0			/* r0: PCIMBR.LOCK bit */	or	r0,r1	mov.l	r1,@r2			/* Update PCIMBR with 16 MB page */	mov.l	@(MMUCR,r3),r1;		/* Replace UTLB entry #63 */	mov.l	MP_X0000FC00,r2;	mov.l	MP_PCI_16M_PN_MASK,r0;	or	r2,r1	mov.l	r1,@(MMUCR,r3)		/* MMUCR.URC = 63 */	mov.l	@(PTEH,r3),r1;		/* r1: VPN | ASID */	mov.l	MP_PCI_1M_PTEL_BASE,r2;	and	r0,r1			/* r1: offset in 16MB PCI window */	or	r2,r1			/* r1: PPN | page attributes */	mov.l	r1,@(PTEL,r3)		/* update PTEL */	ldtlb				/* load PTEH/PTEL to TLB */	nop	rte;				/* UNBLOCK EXCEPTION */	nop			.align	_ALIGN_TEXTMP_XFF000000:		.long	0xff000000MP_PCI_VMEM_LOW:	.long	0x10000000	/*      (to be patched) */MP_PCI_VMEM_HIGH:	.long	0x14000000	/* 64MB (to be patched) */MP_PCI_PMEM_BASE:	.long  -0x10000000	/*      (to be patched) */MP_PCIMBR:		.long	0xfe2001c4MP_X0000FC00:		.long	0x0000fc00MP_PCI_16M_PN_MASK:	.long	0x00fffc00	/* mask to extract page number*/MP_PCI_1M_PTEL_BASE:	.long	0x1d0001f4	/* 0x1d000000 - 0x1dffffff,						 * V, 1MB, RW, NoCache, Dirty */			.align	_ALIGN_TEXTmmuPciStubEnd:			.type	_mmuPciStubSize,@object			.size	_mmuPciStubSize,4_mmuPciStubSize:	.long	mmuPciStubEnd - _mmuPciStub			.type	_mmuPciStubParams,@object			.size	_mmuPciStubParams,4_mmuPciStubParams:	.long	MP_PCI_VMEM_LOW - _mmuPciStub	.align	_ALIGN_TEXT	.type	_mmuPciIoStub,@function_mmuPciIoStub:				/* r1: TEA,  r3: 0xff000000 */	mov.l	MP_PCI_VIO_LOW,r0;	/* Lower PCI I/O space boundary */	mov.l	MP_PCI_VIO_HIGH,r2;	/* Upper PCI I/O space boundary */	cmp/hi	r1,r0	bt	mmuPciIoStubEnd	cmp/hs	r2,r1	bt	mmuPciIoStubEnd	mov.l	MP_XFFFC0000,r2;	mov.l	MP_PCI_PIO_BASE,r0;	and	r2,r1			/* r1: TEA & 0xfffc0000 */	mov.l	MP_PCIIOBR,r2;	add	r0,r1	mov.l	@r2,r0;	and	#1,r0			/* r0: PCIIOBR.LOCK bit */	or	r0,r1	mov.l	r1,@r2			/* Update PCIIOBR with 256KB page */	mov.l	MP_XFFFF03FF,r0;	mov.l	@(MMUCR,r3),r1;		/* Replace UTLB entry #62 */	mov.l	MP_X0000F800,r2;	and	r0,r1	mov.l	MP_PCI_256K_PN_MASK,r0;	or	r2,r1	mov.l	r1,@(MMUCR,r3)		/* MMUCR.URC = 62 */	mov.l	@(PTEH,r3),r1;		/* r1: VPN | ASID */	mov.l	MP_PCI_64K_PTEL_BASE,r2;	and	r0,r1			/* r1: offset in 256KB PCI window */	or	r2,r1			/* r1: PPN | page attributes */	mov.l	r1,@(PTEL,r3)		/* update PTEL */	ldtlb				/* load PTEH/PTEL to TLB */	nop	rte;				/* UNBLOCK EXCEPTION */	nop			.align	_ALIGN_TEXTMP_PCI_VIO_LOW:		.long	0x10000000	/*      (to be patched) */MP_PCI_VIO_HIGH:	.long	0x14000000	/* 64MB (to be patched) */MP_PCI_PIO_BASE:	.long  -0x10000000	/*      (to be patched) */MP_XFFFC0000:		.long	0xfffc0000MP_PCIIOBR:		.long	0xfe2001c8MP_XFFFF03FF:		.long	0xffff03ffMP_X0000F800:		.long	0x0000f800MP_PCI_256K_PN_MASK:	.long	0x0003fc00	/* mask to extract page number*/MP_PCI_64K_PTEL_BASE:	.long	0x1e2401e4	/* 0x1e240000 - 0x1e27ffff,						 * V, 64K, RW, NoCache, Dirty */			.align	_ALIGN_TEXTmmuPciIoStubEnd:			.type	_mmuPciIoStubSize,@object			.size	_mmuPciIoStubSize,4_mmuPciIoStubSize:	.long	mmuPciIoStubEnd - _mmuPciIoStub			.type	_mmuPciIoStubParams,@object			.size	_mmuPciIoStubParams,4_mmuPciIoStubParams:	.long	MP_PCI_VIO_LOW - _mmuPciIoStub	.type	_mmuStubProper,@function	.align	_ALIGN_TEXT_mmuStubProper:	mov	#-10,r0	mov.l	@(PTEH,r3),r1;	/* r1: ABCDEFGHIJKLMNOPQRSTUV00???????? */	shld	r0,r1		/* r1: 0000000000ABCDEFGHIJKLMNOPQRSTUV */	mov.w	MP_X0FFC,r2;	/* r2: 00000000000000000000111111111100 */	mov	#-12,r0	and	r1,r2		/* r2: 00000000000000000000KLMNOPQRST00 */	shld	r0,r1		/* r1: 0000000000000000000000ABCDEFGHIJ */	mov.l	@(TTB,r3),r0;	shll2	r1		/* r1: 00000000000000000000ABCDEFGHIJ00 */	mov.l	@(r0,r1),r0;	/* r0: --> PTELs table */	cmp/eq	#-1,r0	bt	mmuStubProperErr	mov.l	@(r0,r2),r1;	/* r1: PTEL entry to load */	swap.b	r1,r0	tst	#0x01,r0	/* entry invalid if PTEL.V (bit8) is zero */	bt	mmuStubProperErr	mov.l	r1,@(PTEL,r3)	/* update PTEL */	ldtlb			/* load PTEH/PTEL to TLB */	nop	rte;			/* UNBLOCK EXCEPTION */	nopMP_X0FFC:	.word	0x0ffcmmuStubProperErr:		/* failed to find a valid PTEL entry */	mov.l	MP_ExcNonTrapaOffset,r0; 	stc	vbr,r1	add	r1,r0	jmp	@r0;	mov.l	@(EXPEVT,r3),r5			.align	2MP_ExcNonTrapaOffset:	.long	excNonTrapa - _excStub + SH7700_EXC_STUB_OFFSETmmuStubProperEnd:			.type	_mmuStubProperSize,@object			.size	_mmuStubProperSize,4_mmuStubProperSize:	.long	mmuStubProperEnd - _mmuStubProper#endif /* CPU==SH7750 */#elif (CPU==SH7600 || CPU==SH7000)/******************************************************************************** excStub - exception handler (SH7600/SH7000)** NOMANUAL**	   |        |	   |        |		|        |*	   |________|	   |________|		|________|*	96 |   sr   |	   |   sr   |		|   sr   |* 	92 |__ pc __| ESF  |__ pc __| +64  r5->	|__ pc __| +40*	88 |   pr   |	   |   pr   | +60	|   sr   | +36*  sp->	84 |   pr'  |	   |   pr'  | +56	|   pc   | +32*	80 |        | sp-> |        | +52	|  r15   | +28*	76 |        |	   |  r14   | +48	|  r14   | +24*	72 |        |	   |  r13   | +44	|  r13   | +20*	68 |        |	   |  r12   | +40	|  r12   | +16*	64 |        |	   |  r11   | +36	|  r11   | +12*	60 |        |	   |  r10   | +32	|  r10   |  +8*	56 |        |	   |   r9   | +28	|   r9   |  +4*	52 |        |	   |   r8   | +24	|   r8   |  +0*	48 |        |	   |  macl  | +20	|  macl  |*	44 |        |	   |  mach  | +16	|  mach  |*	40 |        |	   |   r7   | +12	|   r7   |*	36 |        |	   |   r6   |  +8	|   r6   |*	32 |        |	   |   r5   |  +4	|   r5   |*	28 |        |	   |   r4   |  +0  sp->	|   r4   |*	24 |        |	   |        |		|   r3   |*	20 |        |	   |        |		|   r2   |*	16 |        |	   |        |		|   r1   |*	12 |        |	   |        |		|   r0   |*	 8 |        |	   |        |		|   pr   |*	 4 |        |	   |        |		|   gbr  |*	 0 |        |	   |        |	REG_SET	|__ vbr _| <-r6*	   |        |	   |        |		|	 |*/	.align	_ALIGN_TEXT	.type	_excStub,@function_excStub:	add	#-4,sp;		mov.l	r14, @-sp	/* save      r14  */	mov.l	r13, @-sp;	mov.l	r12, @-sp	/* save  r13/r12  */	mov.l	r11, @-sp;	mov.l	r10, @-sp	/* save  r11/r10  */	mov.l	r9,  @-sp;	mov.l	r8,  @-sp	/* save   r9/r8   */	sts.l	macl,@-sp;	sts.l	mach,@-sp	/* save macl/mach */	mov.l	r7,  @-sp;	mov.l	r6,  @-sp	/* save   r7/r6   */	mov.l	r5,  @-sp;	mov.l	r4,  @-sp	/* save   r5/r4   */	sts	pr,r4					/* r4: excBsrTbl[] */	mov.l	@(60,sp),r7;	lds	r7,pr		/* restore pr */	mov	sp,r5;		add	#64,r5		/* r5->ESF */				mov.l	r5,@(52,sp)	/* save as r15  */	mov.l	@r5,r6;		mov.l	r6,@(56,sp)	/* save pc      */	mov.l	@(4,r5),r6;	mov.l	r6,@(60,sp)	/* save sr      */	mov.l	r3,@-sp;	mov.l	r2,@-sp		/* save r3/r2   */	mov.l	r1,@-sp;	mov.l	r0,@-sp		/* save r1/r0   */	sts.l	pr,@-sp					/* save pr      */	stc.l	gbr,@-sp;	stc.l	vbr,@-sp	/* save gbr/vbr */							/* (sp --> REG_SET) */	add	#-6,r4			/* adjust return adrs to be BSR adrs  */	mova	_excBsrTblBErr,r0	/*- BUS ERROR INTERRUPT SUPPORT CODE -*/	cmp/eq	r0,r4                   /* is this a bus error interrupt?     */	bt	excBErrExc              /* if yes, do special handling        */					/*------------------------------------*/	mova	_excBsrTbl,r0	sub	r0,r4			/* get offset from start of BSR table */	shlr2	r4			/* turn vector offset into excep num  */excDoProc:				/* do exception processing            */	mov.l	ExcExcHandle,r0		/*   r4: excep num                    */	jsr	@r0			/*   r5: ESF*                         */	mov	sp,r6			/*   r6: REG_SET* (delay slot)        */	add	#8,sp					/* skip vbr&gbr */	lds.l	@sp+,pr					/* restore pr   */	mov.l	@sp+,r0;	mov.l	@sp+,r1		/* restore r0/r1 */	mov.l	@sp+,r2;	mov.l	@sp+,r3		/* restore r2/r3 */	mov.l	@sp+,r4;	mov.l	@sp+,r5		/* restore r4/r5 */	mov.l	@sp+,r6;	mov.l	@sp+,r7		/* restore r6/r7 */	lds.l	@sp+,mach;	lds.l	@sp+,macl	/* restore mach/macl */	add	#40,sp			/* pop REG_SET off stack              */	rte				/* return to task that got exception  */	nop				/* (delay slot) */excBErrExc:                             /*- BUS ERROR INTERRUPT SUPPORT CODE -*/	ldc	r6,sr			/* succeed task's sr value.           */        mov.l   ExcBErrVecNum,r1	/* set bus error excep number in r4,  */        bra     excDoProc		/* then return to normal sequence.    */        mov.l   @r1,r4			/* (delay slot)                       */					/*------------------------------------*/		.align	2ExcExcHandle:	.long	_excExcHandleExcBErrVecNum:	.long	_excBErrVecNum/******************************************************************************** excIntStub - uninitialized interrupt handler (SH7600/SH7000)** NOMANUAL**	<task'sp>	   <task'sp>	   <int stack>		<int stack>**	|        |	   |        |*	|________|	   |________|*	|   sr   |	20 |   sr   |* ESF	|__ pc __|	16 |__ pc __|*	|   pr   |	12 |   pr   |* sp->	|   pr'  |	 8 |   r0   |*	|        |	 4 |   r1   |	   |________|		|________|*	|        |  r1-> 0 |   r2   | <--- |task'sp |		|task'sp |* 	|        |	   |        |	   |   r3   |		|   r3   |*	|        |	   |        |	   |   r4   |		|   r4   |*	|        |	   |        |	   |   r5   |		|   r5   |*	|        |	   |        |	   |   r6   |		|   r6   |*	|        |	   |        |	   |   r7   |		|   r7   |*	|        |	   |        |	   |  mach  |		|  mach  |*	|        |	   |        |	   |  macl  |		|  macl  |*	|        |	   |        | sp-> |_ errno_|     +92	|_ errno_|*	|        |	   |        |	   |   sr   |     +88	|        |*	|        |	   |        |	   |   pc   |     +84* 	|        |	   |        |	   |  r15   | +52 +80*	|        |	   |        |	   |  r14   | +48 +76*	|        |	   |        |	   |  r13   | +44 +72*	|        |	   |        |	   |  r12   | +40 +68*	|        |	   |        |	   |  r11   | +36 +64*	|        |	   |        |	   |  r10   | +32 +60*	|        |	   |        |	   |   r9   | +28 +56*	|        |	   |        |	   |   r8   | +24 +52*	|        |	   |        |	   |  macl  | +20 +48*	|        |	   |        |	   |  mach  | +16 +44*	|        |	   |        |	   |   r7   | +12 +40*	|        |	   |        |	   |   r6   |  +8 +36*	|        |	   |        |	   |   r5   |  +4 +32*	|        |	   |        |	   |   r4   |  +0 +28*	|        |	   |        |	   |   r3   |     +24*	|        |	   |        |	   |   r2   |     +20*	|        |	   |        |	   |   r1   |     +16*	          	             	   |   r0   |     +12*	          	             	   |   pr   |      +8*	          	             	   |   gbr  |      +4*	          	           REG_SET |__ vbr _|      +0*	          	             	   |        |*/	.align	_ALIGN_TEXT	.type	_excIntStub,@function