* void cacheAuRomTextUpdate ()*/	.ent	cacheAuRomTextUpdateFUNC_LABEL(cacheAuRomTextUpdate)	/* Save I-cache parameters */	move	t0,a0	move	t1,a1	/* Check for primary data cache */	blez	a2,99f	/* Flush-invalidate primary data cache */	li	a0,K0BASE	move	a1,a2	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)	sync99:	/* replace I-cache parameters */	move	a2,t0	move	a3,t1		/* Check for primary instruction cache */	blez	a0,99f		/* Invalidate primary instruction cache */	li	a0,K0BASE	move	a1,a2	icacheop(a0,a1,a2,a3,Index_Invalidate_I)	sync99:	j	ra	.end	cacheAuRomTextUpdate/******************************************************************************** cacheAuDCFlushInvalidateAll - flush entire Au data cache** RETURNS: N/A** void cacheAuDCFlushInvalidateAll (void)*/	.ent	cacheAuDCFlushInvalidateAllFUNC_LABEL(cacheAuDCFlushInvalidateAll)	/* run from kseg1 */	la	t0,1f	li	t1,KSEG2_TO_KSEG0_MASK	and	t0,t0,t1	or	t0,K1BASE	j	t01:		/* Check for primary data cache */	lw	a2,cacheAuDCacheSize	blez	a2,99f	/* Flush-invalidate primary data cache */	lw	a3,cacheAuDCacheLineSize	li	a0,K0BASE	move	a1,a2	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)	99:	j	ra	.end	cacheAuDCFlushInvalidateAll/******************************************************************************** cacheAuDCFlushInvalidate - flush Au data cache locations** RETURNS: N/A** void cacheAuDCFlushInvalidate*     (*     baseAddr,		/@ virtual address @/*     byteCount		/@ number of bytes to invalidate @/*     )*/	.ent	cacheAuDCFlushInvalidateFUNC_LABEL(cacheAuDCFlushInvalidate)	/* run from kseg1 */	la	t0,1f	li	t1,KSEG2_TO_KSEG0_MASK	and	t0,t0,t1	or	t0,K1BASE	j	t01:		/* Check for primary data cache */	lw	a2,cacheAuDCacheSize	blez	a2,99f	/* Flush-invalidate primary data cache */	lw	a3,cacheAuDCacheLineSize	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)99:	j	ra	.end	cacheAuDCFlushInvalidate/******************************************************************************** cacheAuICInvalidateAll - invalidate entire Au instruction cache** RETURNS: N/A** void cacheAuICInvalidateAll (void)*/	.ent	cacheAuICInvalidateAllFUNC_LABEL(cacheAuICInvalidateAll)	/* run from kseg1 */	la	t0,1f	li	t1,KSEG2_TO_KSEG0_MASK	and	t0,t0,t1	or	t0,K1BASE	j	t01:		/* Check for primary instruction cache */	lw	a2,cacheAuICacheSize	blez	a2,99f	/* Invalidate primary instruction cache */	lw	a3,cacheAuICacheLineSize	li	a0,K0BASE	move	a1,a2	icacheop(a0,a1,a2,a3,Index_Invalidate_I)99:	j	ra	.end	cacheAuICInvalidateAll/******************************************************************************** cacheAuICInvalidate - invalidate Au instruction cache locations** RETURNS: N/A** void cacheAuICInvalidate*     (*     baseAddr,		/@ virtual address @/*     byteCount		/@ number of bytes to invalidate @/*     )*/	.ent	cacheAuICInvalidateFUNC_LABEL(cacheAuICInvalidate)	/* run from kseg1 */	la	t0,1f	li	t1,KSEG2_TO_KSEG0_MASK	and	t0,t0,t1	or	t0,K1BASE	j	t01:		/* Check for primary instruction cache */	lw	a2,cacheAuICacheSize	blez	a2,99f		/* Invalidate primary instruction cache */	lw	a3,cacheAuICacheLineSize	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)99:	j	ra	.end	cacheAuICInvalidate/******************************************************************************** cacheAuPTextUpdateAll - text update for entire cache.** RETURNS: N/A** void cacheAuPTextUpdateAll (void)*/	.ent	cacheAuPTextUpdateAllFUNC_LABEL(cacheAuPTextUpdateAll)	/* run from kseg1 */	la	t0,1f	li	t1,KSEG2_TO_KSEG0_MASK	and	t0,t0,t1	or	t0,K1BASE	j	t01:		/* Check for primary data cache */	lw	a2,cacheAuDCacheSize	blez	a2,1f	/* Invalidate primary data cache */	li	a0,K0BASE	move	a1,a2	lw	a2,cacheAuDCacheSize	lw	a3,cacheAuDCacheLineSize	icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)1:	/* Check for primary instruction cache */	lw	a2,cacheAuICacheSize	blez	a2,99f	/* Invalidate primary instruction cache */	li	a0,K0BASE	move	a1,a2	lw	a3,cacheAuICacheLineSize	icacheop(a0,a1,a2,a3,Index_Invalidate_I)	99:	j	ra	.end	cacheAuPTextUpdateAll/******************************************************************************** cacheAuPTextUpdate - text update primary caches** RETURNS: N/A** void cacheAuPTextUpdate*     (*     baseAddr,		/@ virtual address @/*     byteCount		/@ number of bytes to invalidate @/*     )*/	.ent	cacheAuPTextUpdateFUNC_LABEL(cacheAuPTextUpdate)	/* run from kseg1 */	la	t0,1f	li	t1,KSEG2_TO_KSEG0_MASK	and	t0,t0,t1	or	t0,K1BASE	j	t01:		/* Check for primary data cache */	lw	a2,cacheAuDCacheSize	blez	a2,1f	/* save input parameters */	move	t0, a0	move	t1, a1		/* Flush-invalidate primary data cache */	lw	a3,cacheAuDCacheLineSize	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)1:	/* Check for primary instruction cache */	lw	a2,cacheAuICacheSize	blez	a2,99f	/* Invalidate primary instruction cache */	move	a0,t0	move	a1,t1	lw	a3,cacheAuICacheLineSize	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)99:	j	ra	.end	cacheAuPTextUpdate/******************************************************************************** cacheAuVirtPageFlush - flush one page of virtual addresses from caches** Change ASID, flush the appropriate cache lines from the D- and I-cache,* and restore the original ASID.** CAVEAT: This routine and the routines it calls MAY be running to clear* cache for an ASID which is only partially mapped by the MMU. For that* reason, the caller may want to lock interrupts.** RETURNS: N/A** void cacheAuVirtPageFlush (UINT asid, void *vAddr, UINT pageSize);*/	.ent	cacheAuVirtPageFlushFUNC_LABEL(cacheAuVirtPageFlush)	/* run from kseg1 */	la	t0,1f	li	t1,KSEG2_TO_KSEG0_MASK	and	t0,t0,t1	or	t0,K1BASE	j	t01:		/* Save parameters */	move	t4,a0			/* ASID to flush */	move	t0,a1			/* beginning VA */	move	t1,a2			/* length */	/*	 * When we change ASIDs, our stack might get unmapped,	 * so use the stack now to free up some registers for use:	 *	t0 - virtual base address of page to flush	 *	t1 - page size	 *	t2 - original SR	 *	t3 - original ASID	 *	t4 - ASID to flush	 */	/* lock interrupts */	mfc0	t2, C0_SR	HAZARD_CP_READ	li	t3, ~SR_INT_ENABLE	and	t3, t2	mtc0	t3, C0_SR	HAZARD_INTERRUPT	/* change the current ASID to context where page is mapped */	mfc0	t3, C0_TLBHI		/* read current TLBHI */	HAZARD_CP_READ	and	t3, 0xff		/* extract ASID field */	beq	t3, t4, 0f		/* branch if no need to change */	mtc0	t4, C0_TLBHI		/* Store new EntryHi  */		HAZARD_TLB0:	/* clear the virtual addresses from D- and I-caches */		lw	a2,cacheAuDCacheSize	blez	a2,1f	/* Flush-invalidate primary data cache */	move	a0, t0	move	a1, t1	lw	a3,cacheAuDCacheLineSize	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)1:	lw	a2,cacheAuICacheSize	blez	a2,1f		/* Invalidate primary instruction cache */	move	a0,t0	move	a1,t1	lw	a3,cacheAuICacheLineSize	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)1:		/* restore the original ASID */	mtc0	t3, C0_TLBHI		/* Restore old EntryHi  */		mtc0	t2, C0_SR		/* restore interrupts */	HAZARD_TLB		j	ra	.end	cacheAuVirtPageFlush/******************************************************************************** cacheAuSync - sync region of memory through all caches** RETURNS: N/A** void cacheAuSync (void *vAddr, UINT pageSize);*/	.ent	cacheAuSyncFUNC_LABEL(cacheAuSync)	/* run from kseg1 */	la	t0,1f	li	t1,KSEG2_TO_KSEG0_MASK	and	t0,t0,t1	or	t0,K1BASE	j	t01:		/* Save parameters */	move	t0,a0			/* beginning VA */	move	t1,a1			/* length */	/* lock interrupts */	mfc0	t2, C0_SR	HAZARD_CP_READ	li	t3, ~SR_INT_ENABLE	and	t3, t2	mtc0	t3, C0_SR	HAZARD_INTERRUPT	/*	 * starting with primary caches, push the memory	 * block out completely	 */	sync	lw	a2,cacheAuICacheSize	blez	a2,1f		/* Invalidate primary instruction cache */	move	a0,t0	move	a1,t1	lw	a3,cacheAuICacheLineSize	vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)1:	lw	a2,cacheAuDCacheSize	blez	a2,1f	/* Flush-invalidate primary data cache */	move	a0, t0	move	a1, t1	lw	a3,cacheAuDCacheLineSize	vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)1:	mtc0	t2, C0_SR		/* restore interrupts */		j	ra	.end	cacheAuSync