cacheR7kDCFlushInvalidate (pDmaBuffer, bytes);	VM_STATE_SET (NULL, pDmaBuffer, bytes,		      MMU_ATTR_CACHE_MSK, MMU_ATTR_CACHE_OFF);	return (pDmaBuffer);	}#endif    }/**************************************************************************** cacheR7kFree - free the buffer acquired by cacheMalloc ()** This routine restores the non-cached buffer to its original state* and does whatever else is necessary to undo the allocate function.** RETURNS: OK, or ERROR if not able to undo cacheMalloc() operation*/LOCAL STATUS cacheR7kFree    (    void * pBuf    )    {    void      * pCacheBuffer;    #ifdef IS_KSEGM    /* Check for unmapped case */    if (IS_KSEG1(pBuf))	{#endif	pCacheBuffer = (void *)K1_TO_K0(pBuf);	pCacheBuffer = (void *)((int)pCacheBuffer - sizeof (void *));	memPartFree (cacheR7kPartId, *(void **)pCacheBuffer);	return (OK);#ifdef IS_KSEGM	}    else	{	BLOCK_HDR * pHdr;		/* pointer to block header */	STATUS	status = OK;	/* return value */	if (vmLibInfo.vmLibInstalled)	    {	    pHdr = BLOCK_TO_HDR (pBuf);	    /*	     * XXX - cache mode is set back to the default one. This may be	     * a problem since we do not know if the original cache mode was either 	     * COPY_BACK or WRITETHROUGH.	     */	    status = VM_STATE_SET (NULL, pBuf, BLOCK_SIZE (pHdr),				   MMU_ATTR_CACHE_MSK, MMU_ATTR_CACHE_DEFAULT);	    }	IOBUF_FREE (pBuf);		/* free buffer after modified */	return (status);	}#endif    }/**************************************************************************** cacheR7kFlush - flush all or some entries in a cache** This routine flushes (writes to memory)  all or some of the entries in the* specified cache.** RETURNS: OK, or ERROR if the cache type is invalid or the cache control* is not supported.*/LOCAL STATUS	cacheR7kFlush    (    CACHE_TYPE	cache,			/* Cache to Invalidate */    void *	pVirtAdrs,		/* Virtual Address */    size_t	bytes 			/* Number of Bytes to Invalidate */    )    {    if (IS_KSEG1(pVirtAdrs))	return (OK);    switch (cache)	{	case DATA_CACHE:	    if (bytes == ENTIRE_CACHE)		cacheR7kDCFlushAll ();	    else		cacheR7kDCFlush (pVirtAdrs, bytes);	    break;	default:	    errno = S_cacheLib_INVALID_CACHE;	    return (ERROR);	    break;        }    return (OK);    }/**************************************************************************** cacheR7kInvalidate - invalidate all or some entries in a cache** This routine invalidates all or some of the entries in the* specified cache.** RETURNS: OK, or ERROR if the cache type is invalid or the cache control* is not supported.*/LOCAL STATUS	cacheR7kInvalidate    (    CACHE_TYPE	cache,			/* Cache to Invalidate */    void *	pVirtAdrs,		/* Virtual Address */    size_t	bytes 			/* Number of Bytes to Invalidate */    )    {    if (IS_KSEG1(pVirtAdrs))	return(OK);    switch (cache)	{	case DATA_CACHE:	    if (bytes == ENTIRE_CACHE)		cacheR7kDCInvalidateAll ();	    else		cacheR7kDCInvalidate (pVirtAdrs, bytes);	    break;	case INSTRUCTION_CACHE:	    if (bytes == ENTIRE_CACHE)		cacheR7kICInvalidateAll ();	    else		cacheR7kICInvalidate (pVirtAdrs, bytes);	    break;	default:	    errno = S_cacheLib_INVALID_CACHE;	    return (ERROR);	    break;        }    return (OK);    }/**************************************************************************** cacheR7kClear - clear all or some entries in a cache** This routine clears all or some of the entries in the* specified cache.** RETURNS: OK, or ERROR if the cache type is invalid or the cache control* is not supported.*/LOCAL STATUS	cacheR7kClear    (    CACHE_TYPE	cache,			/* Cache to clear */    void *	pVirtAdrs,		/* Virtual Address */    size_t	bytes 			/* Number of Bytes to clear */    )    {    if (IS_KSEG1(pVirtAdrs))	return(OK);    switch (cache)	{	case DATA_CACHE:	    if (bytes == ENTIRE_CACHE)		cacheR7kDCFlushInvalidateAll ();	    else		cacheR7kDCFlushInvalidate (pVirtAdrs, bytes);	    break;	case INSTRUCTION_CACHE:	    if (bytes == ENTIRE_CACHE)		cacheR7kICInvalidateAll ();	    else		cacheR7kICInvalidate (pVirtAdrs, bytes);	    break;	default:	    errno = S_cacheLib_INVALID_CACHE;	    return (ERROR);	    break;        }    return (OK);    }/**************************************************************************** cacheR7kVirtToPhys - virtual-to-physical address translation** This routine may be attached to the CACHE_DRV structure virtToPhysRtn* function pointer by cacheR7kMalloc().  This implies that the virtual* memory library is not installed, and that the "cache-safe" buffer has* been created through the use of the R7000 K1 segment.** NOMANUAL*/LOCAL void * cacheR7kVirtToPhys    (    void * address                      /* Virtual address */    )    {    return ((void *) K1_TO_PHYS(address));    }/**************************************************************************** cacheR7kPhysToVirt - physical-to-virtual address translation** This routine may be attached to the CACHE_DRV structure physToVirtRtn* function pointer by cacheR7kMalloc().  This implies that the virtual* memory library is not installed, and that the "cache-safe" buffer has* been created through the use of the R7000 K1 segment.** NOMANUAL*/LOCAL void * cacheR7kPhysToVirt    (    void * address                      /* Physical address */    )    {    return ((void *) PHYS_TO_K1(address));    }/**************************************************************************** cacheR7kTextUpdate - invalidate updated text section** This routine invalidates the specified text section so that* the correct updated text is executed.** NOMANUAL*/LOCAL STATUS cacheR7kTextUpdate    (    void * address,                     /* Physical address */    size_t bytes 			/* bytes to invalidate */    )    {    if ((bytes != ENTIRE_CACHE) &&	((address == NULL) || (bytes == 0) || IS_KSEG1(address)))	return (OK);        if (bytes == ENTIRE_CACHE)	cacheR7kPTextUpdateAll ();    else	cacheR7kPTextUpdate (address, bytes);    return (OK);    }/**************************************************************************** cacheR7kPipeFlush - flush R7000 write buffers to memory** This routine forces the processor output buffers to write their contents* to RAM.  A cache flush may have forced its data into the write buffers,* then the buffers need to be flushed to RAM to maintain coherency.* It simply calls the sysWbFlush routine from the BSP.** RETURNS: OK.** NOMANUAL*/LOCAL STATUS cacheR7kPipeFlush (void)    {    sysWbFlush ();    return (OK);    }