/* cacheALib.s - ARM cache management assembly routines *//* Copyright 1996-2001 Wind River Systems, Inc. *//*modification history--------------------01q,11feb03,jb  Fix Merge generated problems01p,17dec02,jb  Adding ARM 926e and ARM 102xE support, really fixed SPR 7179501r,31jan03,jb   Backing out SPR 82859 fix as it breaks wrPpmci8031001q,29jan03,jb   Resolve SPR 7179501p,29jan03,scm  SPR 82859 modification...01o,07dec01,rec  Merge in changes from Tor 2.1.1                 removed early enable of ints in 920T DClearDisable (SPR                 #71795)01n,17oct01,t_m  convert to FUNC_LABEL:01m,11oct01,jb   Enabling removal of pre-pended underscores for new compilers                 (Diab/Gnu elf)01k,03oct01,jpd  corrected ARM946E code (SPR #68958).01l,25jul01,scm  add btbInvalidate routine and remove legacy test code from                 cacheDFlush/cacheDFlushAll for XScale01k,23jul01,scm  change XScale name to conform to coding standards...01j,21jul00,jpd  added support for ARM946E.01i,15feb99,jpd  added support for ARM740T, ARM720T, ARM920T.01h,24nov98,jpd  added support for ARM 940T, SA-1100/SA-1500; made		 cacheArchPipeFlush return OK (SPR #22258); made Thumb-aware;		 moved cacheArchIntLock() to cacheALib2.s;	    cdp  added support for generic ARM ARCH3/ARCH4.01g,14nov97,jpd  disabled Ints in SA-110 cacheDClearAll.01f,31oct97,jpd  fixed faults with invalidation on 810.01e,27oct97,kkk  took out "***EOF***" line from end of file.01d,10oct97,jpd  Tidied L$_ usage.01c,18sep97,jpd  Changed 810 code in line with ARM 810 errata sheet.		 Added use of sysCacheFlushReadArea on SA-110. Added		 cacheIMBRange(). Only use cacheArchIntMask in long		 cache operations.  Added soft-copy of MMU CR on 710A.		 Changed .aligns to .baligns.  Corrected error in use		 of cacheArchIntMask and made L$_cacheArchIntMask		 declaration not specific to ARMSA110.01b,20feb97,jpd  tidied comments/documentation.01a,18oct96,jpd  written, based on 68K version 01p.*//*DESCRIPTIONThis library contains routines to control ARM Ltd.'s caches.N.B.Although this library contains code written for the ARM810 CPU, at the timeof writing, this code has not been tested fully on that CPU.YOU HAVE BEEN WARNED.INTERNALTO keep these routines as efficient as possible, they no longer all generatestack frames.INCLUDE FILES: cacheLib.hSEE ALSO: cacheLib,.I "ARM Architecture Reference Manual,".I "ARM 710A Data Sheet,".I "ARM 810 Data Sheet,".I "ARM 940T Technical Reference Manual,".I "ARM 946E-S Technical Reference Manual,".I "ARM 740T Data Sheet,".I "ARM 720T Data Sheet,".I "ARM 920T Technical Reference Manual,".I "ARM 926EJ-S Technical Reference Manual,".I "ARM 1020E Technical Reference Manual,".I "ARM 1022E Technical Reference Manual,".I "Digital Semiconductor SA-110 Microprocessor Technical Reference Manual,".I "Digital Semiconductor SA-1100 Microprocessor Technical Reference Manual,".I "Digital Semiconductor SA-1500 Mediaprocessor Data Sheet."*/#define _ASMLANGUAGE#include "vxWorks.h"#include "asm.h"#include "cacheLib.h"#include "arch/arm/mmuArmLib.h"	.data	.globl  FUNC(copyright_wind_river)	.long   FUNC(copyright_wind_river)	/* globals */#ifndef ARMCACHE#error ARMCACHE not defined#endif#if (ARMCACHE == ARMCACHE_1020E)#define ARMCACHE_1020E_REV0_DRAIN_WB TRUE#define ARMCACHE_1020E_REV0_MCR_CP15 TRUE#else#define ARMCACHE_1020E_REV0_DRAIN_WB FALSE#define ARMCACHE_1020E_REV0_MCR_CP15 FALSE#endif/* * Only the following processors are supported by this library. Others * should not be assembling this file, but, if they do, ensure they get no code. */#if ((ARMCACHE == ARMCACHE_710A)   || (ARMCACHE == ARMCACHE_720T)   || \     (ARMCACHE == ARMCACHE_740T)   || (ARMCACHE == ARMCACHE_810)    || \     (ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_920T)   || \     (ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_940T)   || \     (ARMCACHE == ARMCACHE_946E)   || (ARMCACHE == ARMCACHE_XSCALE) || \     (ARMCACHE == ARMCACHE_1020E)  |  (ARMCACHE == ARMCACHE_1022E))#if ((ARMCACHE == ARMCACHE_810)    || (ARMCACHE == ARMCACHE_SA110)  || \     (ARMCACHE == ARMCACHE_SA1100) || (ARMCACHE == ARMCACHE_SA1500) || \     (ARMCACHE == ARMCACHE_920T)   || (ARMCACHE == ARMCACHE_926E)   || \     (ARMCACHE == ARMCACHE_940T)   || (ARMCACHE == ARMCACHE_946E)   || \     (ARMCACHE == ARMCACHE_XSCALE) || (ARMCACHE == ARMCACHE_1020E)  || \     (ARMCACHE == ARMCACHE_1022E))	/* Not needed on 710A, 740T, 720T, as they are write-through */	.globl	FUNC(cacheDFlush)		/* Flush D-cache entry */	.globl	FUNC(cacheDFlushAll)		/* Flush D-cache and drain W/B */#endif	.globl	FUNC(cacheDInvalidateAll)	/* Invalidate all D-cache */#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_920T)   || \     (ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_946E)   || \     (ARMCACHE == ARMCACHE_XSCALE) || (ARMCACHE == ARMCACHE_1020E)  || \     (ARMCACHE == ARMCACHE_1022E))	/* not supported on 710A, 810, 940T, 740T, 720T */	.globl	FUNC(cacheDInvalidate)	/* Invalidate D-cache entry */#endif#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_920T)   || \     (ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_940T)   || \     (ARMCACHE == ARMCACHE_946E)   || (ARMCACHE == ARMCACHE_XSCALE) || \     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))	.globl	FUNC(cacheIInvalidateAll)	/* Invalidate all I-cache */#endif#if ((ARMCACHE == ARMCACHE_920T)   || (ARMCACHE == ARMCACHE_926E) || \     (ARMCACHE == ARMCACHE_940T)   || (ARMCACHE == ARMCACHE_946E) || \     (ARMCACHE == ARMCACHE_XSCALE) || (ARMCACHE == ARMCACHE_1020E) || \     (ARMCACHE == ARMCACHE_1022E))	.globl	FUNC(cacheIInvalidate)	/* Invalidate I-cache entry */#if (ARMCACHE == ARMCACHE_XSCALE)        .globl  FUNC(btbInvalidate)          /* Invalidate BTB */#endif#endif	.globl	FUNC(cacheDClearDisable)	/* Clear, disable D-cache, W/B */#if ((ARMCACHE == ARMCACHE_810)    || (ARMCACHE == ARMCACHE_SA110)  || \     (ARMCACHE == ARMCACHE_SA1100) || (ARMCACHE == ARMCACHE_SA1500) || \     (ARMCACHE == ARMCACHE_920T)   || (ARMCACHE == ARMCACHE_926E)   || \     (ARMCACHE == ARMCACHE_940T)   || (ARMCACHE == ARMCACHE_946E)   || \     (ARMCACHE == ARMCACHE_XSCALE) || (ARMCACHE == ARMCACHE_1020E)  || \     (ARMCACHE == ARMCACHE_1022E))	/* not supported on 710A, 740T, 720T */	.globl	FUNC(cacheDClear)		/* Clear D-cache entry */#endif	.globl	FUNC(cacheDClearAll)		/* Clear D-cache, drain W/B */#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_920T)   || \     (ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_940T)   || \     (ARMCACHE == ARMCACHE_946E)   || (ARMCACHE == ARMCACHE_XSCALE) || \     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))	/* not supported on 710A, 810, 740T, 720T */	.globl	FUNC(cacheIClearDisable)	/* Disable and clear I-cache */#endif	.globl	FUNC(cacheArchPipeFlush)	/* Drain Write buffer */#if ARMCACHE_NEEDS_IMB	.globl	FUNC(cacheIMB)		/* Execute IMB to flush Prefetch Unit */	.globl	FUNC(cacheIMBRange)		/* IMBRange to flush some of PU */#endif#if ((ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_946E) || \     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))	.globl	FUNC(cacheIdentify)		/* Get types/sizes of caches fitted */#endif /* (ARMCACHE == ARMCACHE_926E,946E,1020E,1022E) */#if (ARMCACHE == ARMCACHE_XSCALE)	/* currently only supported by XScale platform */	.globl  FUNC(cacheIFetchNLock)       /* fetch and lock instruction cache line */	.globl  FUNC(cacheIUnLock)           /* unlock instruction cache */	.globl  FUNC(cacheDSetLockMode)      /* set data cache lock mode */	.globl  FUNC(cacheDLockRead)         /* read data cache lock mode */	.globl  FUNC(cacheDUnLock)           /* ignore mode, unlock data cache */	.globl  FUNC(tlbILock)               /* translate and lock instruction TLB entry */	.globl  FUNC(tlbIUnLock)             /* unlock instruction TLB entry */	.globl  FUNC(tlbDLock)               /* translate and lock data TLB entry */	.globl  FUNC(tlbDUnLock)             /* unlock data TLB entry */	.globl FUNC(cacheCreateInternalDataRAM) /* cache as Internal Data RAM */	.globl FUNC(cacheLockDataIntoDataCache) /* allow the ability to lock data into data cache */#endif	/* externals */#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_XSCALE))	/*	 * Address of (declared in BSP) a readable, cached block of	 * address space used for nothing else, which we will read to	 * force the D-cache to be written out to memory.  If the BSP has	 * an area of the address space which is usable for this purpose,	 * which does not actually contain memory, it should set the	 * address to that area. If it does not, it should allocate some	 * RAM for this. In either case, the area must be marked as	 * readable and cacheable in the page tables.	 */	.extern	FUNC(sysCacheFlushReadArea)#endif /* ARMCACHE == ARMCACHE_SA110,SA1100,SA1500,XSCALE */#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_XSCALE))	/*	 * Same for the minicache. The area must be marked as readable	 * and minicacheable in the page tables.	 */	.extern	FUNC(sysMinicacheFlushReadArea)#endif /* ARMCACHE == SA110,SA1100,SA1500,XSCALE */#if ((ARMCACHE == ARMCACHE_926E) || (ARMCACHE == ARMCACHE_940T))        /*         * All ARM 926E and 940T BSPs, must define the variable         * sysCacheUncachedAdrs which contains the address of a word that         * is uncached and is safe to read (i.e. has no side effects).         *         * On 940T, this is used by the cacheLib code to perform a read         * (only) to drain the write-buffer. Clearly this address must be         * present within one of the valid regions, where it must be marked as         * non-cacheable.         *         * On 926E, this is used to synchronise the data and         * instruction streams in Level 2 AHB subsystems. The address         * must be marked as valid and non-cacheable,         */        .extern FUNC(sysCacheUncachedAdrs)#endif /* ARMCACHE == ARMCACHE_926E, 940T */#if ((ARMCACHE == ARMCACHE_946E) || (ARMCACHE == ARMCACHE_1020E) || \     (ARMCACHE == ARMCACHE_1022E))	.extern FUNC(cacheArchIndexMask)	/* mask to get index number from adrs */#endif /* (ARMCACHE == ARMCACHE_946E,1020E,1022E) */#if (ARMCACHE == ARMCACHE_1020E) || (ARMCACHE == ARMCACHE_1022E)        .extern  FUNC(cacheArchSegMask)       /* mask to get segment num from adrs */#endif /* (ARMCACHE == ARMCACHE_1020E,1022E) */#if ((ARMCACHE == ARMCACHE_710A) || (ARMCACHE == ARMCACHE_720T) || \     (ARMCACHE == ARMCACHE_740T) || (ARMCACHE == ARMCACHE_810))	/* variables */	.data	.balign	1	/* variable used with a SWPB instruction to drain the write-buffer */FUNC_LABEL(_cacheSwapVar)	.byte	0#endif /* ARMCACHE == ARMCACHE_710A, 720T, 740T, 810 */	.text	.balign	4/******************************************************************************//* PC-relative-addressable symbols - LDR Rn, =sym was (is?) broken */#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_XSCALE))L$_sysCacheFlushReadArea:	.long	FUNC(sysCacheFlushReadArea)#endif /* ARMCACHE == ARMCACHE_SA110,SA1100,SA1500,XSCALE */#if ((ARMCACHE == ARMCACHE_SA1100) || (ARMCACHE == ARMCACHE_SA1500) || \     (ARMCACHE == ARMCACHE_XSCALE))L$_sysMinicacheFlushReadArea:	.long	FUNC(sysMinicacheFlushReadArea)#endif /* ARMCACHE == SA1100,SA1500,XSCALE */#if ((ARMCACHE == ARMCACHE_926E) || (ARMCACHE == ARMCACHE_940T))L$_sysCacheUncachedAdrs:	.long	FUNC(sysCacheUncachedAdrs)#endif /* ARMCACHE == ARMCACHE_926E, 940T */L$_cacheArchIntMask:	.long	FUNC(cacheArchIntMask)#if ((ARMCACHE == ARMCACHE_710A) || (ARMCACHE == ARMCACHE_720T) || \     (ARMCACHE == ARMCACHE_740T) || (ARMCACHE == ARMCACHE_810))L$_cacheSwapVar:	.long	FUNC(_cacheSwapVar)#endif#if (ARMCACHE == ARMCACHE_710A)L$_mmuCrValue:	.long	FUNC(_mmuCrValue)#endif#if ((ARMCACHE == ARMCACHE_946E) || (ARMCACHE == ARMCACHE_1020E) || \     (ARMCACHE == ARMCACHE_1022E))L$_cacheArchIndexMask:	.long	FUNC(cacheArchIndexMask)	/* mask to get index number from adrs */#endif /* (ARMCACHE == ARMCACHE_946E,1020E,1022E) */#if (ARMCACHE == ARMCACHE_1020E) || (ARMCACHE == ARMCACHE_1022E)L$_cacheArchSegMask:        .long   FUNC(cacheArchSegMask)       /* mask to get segment num from adrs */#endif /* (ARMCACHE == ARMCACHE_1020E,1022E) *//********************************************************************************* cacheDClearDisable - clear, flush, disable D-cache and Write buffer (ARM)** This routine clears (flushes and invalidates) and disables the D-cache,* disables the write-buffer and drains it.** NOMANUAL** RETURNS: N/A** void cacheDClearDisable (void)*/_ARM_FUNCTION_CALLED_FROM_C(cacheDClearDisable)/* * Most CPUs will need their caches cleared, the 710, 740T, 720T just * needs the W/B drained. We must close any window between cleaning and * invalidating the caches and disabling them (as best we can). */#if ((ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) ||\     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_XSCALE))	LDR	r0, L$_sysCacheFlushReadArea	ADD	r1, r0, #D_CACHE_SIZE	LDR	r2, L$_cacheArchIntMask	/* Get pointer to cacheArchIntMask */	LDR	r2, [r2]		/* get cacheArchIntMask */	MRS	r3, cpsr		/* Get CPSR */	ORR	r2, r3, r2		/* disable interrupts */	MSR	cpsr, r20:	LDR	r2, [r0], #_CACHE_ALIGN_SIZE /* Displace cache entries */	TEQS	r1, r0			/* Reached end of buffer? */	BNE	0b			/* Branch if not */#endif#if ((ARMCACHE == ARMCACHE_SA1100) || (ARMCACHE == ARMCACHE_SA1500) || \     (ARMCACHE == ARMCACHE_XSCALE))	LDR	r0, L$_sysMinicacheFlushReadArea