/* cacheArchLib.c - ARM cache support library *//* Copyright 1996-2001 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01v,17dec02,jb   Adding ARM 926e and ARM 102xE support01v,20jan03,jb   Resolve SPR 8203701u,13nov01,to   hand over global variables to cacheArchVars.c,		 synchronize with AE, style and spelling fix,		 initialise (UK) -> initialize (US), etc.01t,03oct01,jpd  corrected ARM946E code (SPR #68958).01s,26sep01,scm  XScale should support CACHE_WRITETHROUGH...01r,19sep01,scm  XScale compatibility with visionProbe requires full                 instruction cache flush instead of single line flush...01q,25jul01,scm  add support for btbInvalidate...01p,23jul01,scm  change XScale name to conform to coding standards...01o,21jul00,jpd  added support for ARM946E.01n,04apr00,jpd  fix bug in 920T cacheInvalidate SPR #30698 and cacheDmaMalloc		 SPR #30697.01m,26oct99,jpd  cacheArchLibInstall documentation changes.01l,10sep99,jpd  add support for ARM740T, ARM720T, ARM920T.01k,21jan99,jpd  documentation changes.01j,20jan99,cdp  removed support for old ARM libraries.01i,24nov98,jpd  add support for ARM 940T, SA-1100, SA-1500; add variable		 cacheArchAlignSize; added option not to disable I-cache on		 SA-1500; removed use of mmuIntLock; vmBaseLib cacheDmaFree now		 marks buffer cacheable (SPR #22407); add cacheArchLibInstall();            cdp  added support for generic ARM ARCH3/ARCH4.01h,09mar98,jpd  added cacheLib.dmaVirtToPhys etc. setting.01g,31oct97,jpd  fixed cache invalidation faults on 810.01f,27oct97,kkk  took out "***EOF***" line from end of file.01e,10oct97,jpd  Restrict include of dsmArmLib.h to 810.01d,18sep97,jpd  Check SWI vector initialised before issuing IMB. Add		 use of IMBRange. Defer setting of cacheDataEnabled,		 when MMU is off. Modified FIQ protection, added		 BSP-specific cache flush area. Added ARM7TDMI_T		 support. Made cacheArchState, cacheArchIntMask not		 specific to ARMSA110.01c,03mar97,jpd  Tidied comments/documentation.01b,29jan97,jpd  Added dummy cacheArchLibInit for ARM7TDMI.01a,04sep96,jpd  written, based on Am29K version 01c and 68k version 03j*//*DESCRIPTIONThis library contains architecture-specific cache library functions for theARM family instruction and data caches.  The various members of the ARMfamily of processors support different cache mechanisms; thus, someoperations cannot be performed by certain processors because they lackparticular functionalities.  In such cases, the routines in thislibrary return ERROR.  Processor-specific constraints are addressed inthe manual entries for routines in this library.  If the caches areunavailable or uncontrollable, the routines return ERROR.STRONGARM CACHE FLUSHINGOn ARM SA-110, the BSP must provide the (virtual) address(sysCacheFlushReadArea) of a readable, cached block of address space,used for nothing else, which will be read to force the D-cache to bewritten out to memory.  If the BSP has an area of the address spacewhich is usable for this purpose, which does not actually containmemory, it should set the pointer to that area.  If it does not, itshould allocate some RAM for this. In either case, the area must bemarked as readable and cacheable in the page tables.On ARM SA-1100/ARM SA-1500, in addition to sysCacheFlushReadArea, theBSP must provide the (virtual) address (sysMinicacheFlushReadArea) of areadable, block of address space, marked as minicacheable, used fornothing else, which will be used to force the minicache to be writtenout to memory.ARM 940TThe BSP must declare a pointer (sysCacheUncachedAdrs) to a readable,uncached word of address space used for reading, to drain thewrite-buffer.  The area containing this address must be marked as validand non-cacheable, and the address must be safe to read, i.e. have noside-effects.ARM 926EJ-SThe BSP must declare a pointer (sysCacheUncachedAdrs) to a readable,uncached word of address space used for reading, to synchronise thedata and instruction streams in Level 2 AHB subsystems. The addressmust be marked as valid and non-cacheable, and the address must be safeto read, i.e. have no side-effects.INTERNALAlthough this library contains code written for the ARM810 CPU, at thetime of writing, this code has not been tested fully on that CPU.(YOU HAVE BEEN WARNED).NOTEAll caching functions on the ARM require the MMU to be enabled,except for XSCALE, StrongARM, ARM920T, ARM926E and ARM1020E, wherethe I-cache can be enabled without enabling the MMU.  No specificsupport for this mode of operation is included.INTERNALThere are some terminology problems. VxWorks uses the following definitions:Clear = VxWorks "Flush" then VxWorks "Invalidate"Flush = write out to memory = ARM "clean"Invalidate = make cache entry invalid = ARM "flush"INTERNALThe cache enable and disable processes consist of the following actions,executed by cacheArchEnable() and cacheArchDisable().  To enablea disabled cache, first the cache is fully invalidated.  Then the cache mode(write-through, copy-back, etc.) is configured.  Finally, the cache is turnedon.  Enabling an already enabled cache results in no operation.INTERNALTo disable an enabled cache, first the cache is invalidated.  However, a cacheconfigured in copy-back mode must first have been pushed out to memory.  Onceinvalidated, the cache is turned off.  Disabling an already disabled cacheresults in no operation.For general information about caching, see the manual entry for cacheLib.INCLUDE FILES: cacheLib.h, mmuLib.hSEE ALSO: cacheLib, vmLib,.I "ARM Architecture Reference Manual,".I "ARM 710A Data Sheet,".I "ARM 810 Data Sheet,".I "Digital Semiconductor SA-110 Microprocessor Technical Reference Manual,".I "Digital Semiconductor SA-1100 Microprocessor Technical Reference Manual,".I "Digital Semiconductor SA-1500 Mediaprocessor Data Sheet,".I "ARM 720T Data Sheet,".I "ARM 740T Data Sheet,".I "ARM 920T Technical Reference Manual,".I "ARM 926EJ-S Technical Reference Manual,".I "ARM 940T Technical Reference Manual.".I "ARM 1020E Technical Reference Manual.".I "ARM 1022E Technical Reference Manual."*//* includes */#include "vxWorks.h"#if !defined(ARMCACHE)#error ARMCACHE not defined#endif#include "errnoLib.h"#include "cacheLib.h"#include "arch/arm/mmuArmLib.h"#include "arch/arm/intArmLib.h"#if ARMCACHE_NEEDS_IMB#include "arch/arm/dsmArmLib.h"#include "arch/arm/excArmLib.h"#endif#include "stdlib.h"#include "private/memPartLibP.h"#include "private/vmLibP.h"#include "private/funcBindP.h"#include "intLib.h"/* externals */#if (ARM_HAS_MPU)IMPORT int ffsMsb (UINT32 val);#endif/* * The following variables are declared outside this file in a file that is * not compiled in a manner such that variables end up with different names. */IMPORT FUNCPTR	sysCacheLibInit;IMPORT UINT32	cacheArchState;/* * Globals. * * Those globals which have values assigned to them in cacheArchLibInit(), * need to be predefined, else they may be put in BSS.  Since BSS is not * cleared until after cacheArchLibInit() has been called, this would be a * problem. */#if ((ARMCACHE == ARMCACHE_926E)   ||  (ARMCACHE == ARMCACHE_946E)  || \     (ARMCACHE == ARMCACHE_1020E)  ||  (ARMCACHE == ARMCACHE_1022E))#if ((ARMCACHE == ARMCACHE_946E)   || (ARMCACHE == ARMCACHE_1020E) || \     (ARMCACHE == ARMCACHE_1022E))/* * Mask to get cache index number from address. As it happens, this is * also the number we can use in the cache Flush/Clean code, to build * index/segment format values, as it corresponds to the largest index * number, already shifted to the correct place within the word. */UINT32  cacheArchIndexMask = 0;#if (ARMCACHE == ARMCACHE_1020E) || (ARMCACHE == ARMCACHE_1022E)UINT32  cacheArchSegMask = 0;#endif#endif /* (ARMCACHE == ARMCACHE_946E, 1020E, 1022E) */LOCAL UINT32 cacheDCacheSize = 0;LOCAL UINT32 cacheICacheSize = 0;#define D_CACHE_SIZE cacheDCacheSize#define I_CACHE_SIZE cacheICacheSize#endif /* (ARMCACHE == ARMCACHE_926E, 946E, 1020E, 1022E) *//* forward declarations */LOCAL STATUS cacheArchLibInit (CACHE_MODE instMode, CACHE_MODE dataMode);#if ((ARMCACHE == ARMCACHE_710A)   || (ARMCACHE == ARMCACHE_720T)   || \     (ARMCACHE == ARMCACHE_740T)   || (ARMCACHE == ARMCACHE_810)    || \     (ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_920T)   || \     (ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_940T)   || \     (ARMCACHE == ARMCACHE_946E)   || (ARMCACHE == ARMCACHE_XSCALE) || \     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))LOCAL STATUS	cacheArchEnable (CACHE_TYPE cache);LOCAL STATUS	cacheArchDisable (CACHE_TYPE cache);LOCAL STATUS	cacheArchFlush (CACHE_TYPE cache, void * address, size_t bytes);LOCAL STATUS	cacheArchInvalidate (CACHE_TYPE cache, void * address,				     size_t bytes);LOCAL STATUS	cacheArchClear (CACHE_TYPE cache, void * address, size_t bytes);LOCAL STATUS	cacheArchTextUpdate (void * address, size_t bytes);LOCAL void *	cacheArchDmaMalloc (size_t bytes);LOCAL STATUS	cacheArchDmaFree (void * pBuf);LOCAL STATUS	cacheProbe (CACHE_TYPE cache);LOCAL BOOL	cacheIsOn (CACHE_TYPE cache);LOCAL BOOL	cacheMmuIsOn (void);#endif#if ((ARMCACHE == ARMCACHE_740T)   || (ARMCACHE == ARMCACHE_810)  || \     (ARMCACHE == ARMCACHE_920T)   || (ARMCACHE == ARMCACHE_926E) || \     (ARMCACHE == ARMCACHE_940T)   || (ARMCACHE == ARMCACHE_946E) || \     (ARMCACHE == ARMCACHE_XSCALE) || (ARMCACHE == ARMCACHE_1020E) || \     (ARMCACHE == ARMCACHE_1022E))/* * Cache locking capability is only present in hardware on these CPUs and * is not yet implemented. */#if FALSELOCAL STATUS	cacheArchLock (CACHE_TYPE cache, void * address, size_t bytes);LOCAL STATUS	cacheArchUnlock (CACHE_TYPE cache, void * address,				 size_t bytes);#endif#endif/* * Do not support the use of Branch Prediction yet, as we have not had time to * test it properly */#undef BPRED_SUPPORT/********************************************************************************* cacheArchLibInstall - install specific ARM cache library** This routine is provided so that a call to this routine selects the* specific cache library.  It also allows any virtual <-> physical address* translation routines provided by the BSP to be passed to the cache* library as parameters rather than as global data.  These are then used by* cacheDrvVirtToPhys() and cacheDrvPhysToVirt().** If the default address map is such that virtual and physical* addresses are identical (this is normally the case with BSPs), the* parameters to this routine can be NULL pointers.  Only where the* default memory map is such that virtual and physical addresses are* different, need the translation routines be provided.** If the address map is such that the mapping described within the* sysPhysMemDesc structure of the BSP is accurate, then the parameters to* this routine can be mmuPhysToVirt and mmuVirtToPhys: two routines* provided within the architecture code that perform the conversion based* on the information within that structure.  If that assumption is not* true, then the BSP must provide its own translation routines.** RETURNS: N/A** The specification of the translation routines is as follows:** void * virtToPhys*     (*     void *	virtAddr  /@ virtual addr to be translated @/*     )** RETURNS: the physical address** void * physToVirt*     (*     void *	physAddr  /@ physical addr to be translated @/*     )** RETURNS: the virtual address** The caching capabilities and modes for different cache types vary* considerably (see below).  The memory map is BSP-specific and some* functions need knowledge of the memory map, so they have to be provided* in the BSP.  Moreover, now that chips are being made on a* "mix-and-match" basis, selection of the cache type is now a BSP issue.** ARM 7TDMI* No cache or MMU at all (in ARM or Thumb state).  Dummy routine* provided, so that INCLUDE_CACHE_SUPPORT can be defined (the default BSP* configuration).** ARM 710A, 720T AND ARM 740T* Combined instruction and data cache. Actually a write-through cache,* but separate write-buffer could be considered to make this a* copy-back cache if the write-buffer is enabled.  Use the* write-through/copy-back argument to decide whether to enable write* buffer globally.  Marking individual pages (using the MMU) as* write-through or copy-back will control the use of the write-buffer for* those pages if the write-buffer is enabled. Data and instruction cache* modes must be identical.** ARM 810* Combined instruction and data cache.  Write-through and copy-back cache* modes, but separate write-buffer could be considered to make even* write-through a copy-back cache as all writes are buffered, when cache* is enabled. Data and instruction cache modes must be identical.** ARM SA-110* Separate instruction and data caches.  Cache hardware only supports* copy-back mode for data cache.** ARM SA-1100/SA-1110* Separate instruction and data caches.  Cache hardware only supports* copy-back mode for data cache.  D-cache is 8 kbytes in size as* opposed to 16 kbytes for SA-110 and SA-1500.  Minicache of 512 bytes.** ARM SA-1500* Separate instruction and data caches.  Cache hardware only supports* copy-back mode for data cache.  Minicache of 1 kbytes.** ARM 920T, 926E, 1020E, 1022E, AND 946E XSCALE* Separate instruction and data caches.  The global mode of the data* cache cannot be configured and must be copy-back.  Individual pages* can be marked (using the MMU) as write-through or copy-back but* separate write-buffer (which is always enabled) is used for all* cacheable writes (even write-through).  The cache replacement* algorithm can be set to be random or round-robin in hardware.  No* reliance on the method should be present in this code, but it has only* been tested in the default state (random replacement).** ARM 940T* As 920T, but no configurable cache-replacement algorithm.** INTERNAL* This routine is called (from sysHwInit0()), before cacheLibInit() has* been called, before sysHwInit has been called, and before BSS has been* cleared.**/void cacheArchLibInstall    (    void * (physToVirt) (void *), /* phys to virt addr translation rtn */    void * (virtToPhys) (void *)  /* virt to phys addr translation rtn */    )    {    static BOOL initialized = FALSE;    /* protect against being called twice */    if (initialized)	return;    /*     * Normally, cacheArchDmaMalloc() will return addresses with the     * same virtual to physical address mapping as the rest of the system     * (which is normally identical), so the following two routines do     * not need to be provided.  However, on some systems it is not     * possible for a memory mapping to be created where virtual and     * physical addresses are identical.  In that case, the BSP will     * provide routines to perform this mapping, and we should use     * them.     */    cacheLib.dmaPhysToVirtRtn	= (FUNCPTR) physToVirt;    cacheLib.dmaVirtToPhysRtn	= (FUNCPTR) virtToPhys;    /*     * Initialize the function pointer so that the     * architecture-independent code calls the correct code.     */    sysCacheLibInit = cacheArchLibInit;    initialized = TRUE;    return;    }/********************************************************************************* cacheArchLibInit - initialize ARM cache library function pointers** This routine initializes the cache library for ARM processors.  It* initializes the function pointers and configures the caches to the* specified cache modes.  Modes should be set before caching is* enabled.  If two complementary flags are set (enable/disable), no* action is taken for any of the input flags.** NOTE* This routine should not be called directly from cacheLibInit() on the* new (generic) architectures.  Instead, cacheArchLibInstall() should* be called.** INTERNAL* This routine is called (from cacheLibInit()), before sysHwInit has* been called, and before BSS has been cleared.** RETURNS: OK always**/LOCAL STATUS cacheArchLibInit    (    CACHE_MODE	instMode,	/* instruction cache mode */    CACHE_MODE	dataMode	/* data cache mode */    )    {    static BOOL initialized = FALSE;#if ((ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_946E)   || \     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))    UINT32 temp, temp2, temp3;#endif    /* protect (silently) against being called twice */    if (initialized)	return OK;#if ((ARMCACHE == ARMCACHE_710A)   || (ARMCACHE == ARMCACHE_720T)   || \     (ARMCACHE == ARMCACHE_740T)   || (ARMCACHE == ARMCACHE_810)    || \     (ARMCACHE == ARMCACHE_SA110)  || (ARMCACHE == ARMCACHE_SA1100) || \     (ARMCACHE == ARMCACHE_SA1500) || (ARMCACHE == ARMCACHE_920T)   || \     (ARMCACHE == ARMCACHE_926E)   || (ARMCACHE == ARMCACHE_940T)   || \     (ARMCACHE == ARMCACHE_946E)   || (ARMCACHE == ARMCACHE_XSCALE) || \     (ARMCACHE == ARMCACHE_1020E)  || (ARMCACHE == ARMCACHE_1022E))    /*     * Initialize the variable that we want others to use in preference     * to the symbolic constant. Set it to the cache-type-specific value.     */