/* dbgArchLib.c - architecture-dependent debugger library */  /* Copyright 1984-2002 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01q,13nov02,hdn  added doc for x86 hardware breakpoint (spr 79232, 79234)01p,05jun02,wsl  remove references to SPARC and i96001o,26nov01,hdn  updated the x86 section01n,22nov01,hbh  Updated for simulatorrs.01m,16nov01,tlc  Update for MIPS architecture.01l,30oct01,zl   corrected arch names in library description, updated SH                 section.01k,03mar00,zl   merged SH support into T201j,27feb97,jpd  Added ARM-specific documentation.01i,25nov95,jdi  removed 29k stuff.01h,10oct95,jdi  doc: changed .tG Shell back to .pG "Target Shell".01g,06oct95,jdi  changed Debugging .pG's to .tG Shell.01f,12mar95,dvs  changed sr() to srShow() for am29k (SPR #4084) and gr() -> 		 grShow() for consistancy.01e,10feb95,jdi  changed 80960 to i960; synchronized with ../<arch>/dbgArchLibs.01d,27jan95,rhp  added MIPS R3000/R4000 and Intel i386/i486;                 minor doc cleanup on Am29K.01c,02dec93,pme  added Am29K family support.01b,14mar93,jdi  changed underscores in fsrShow() and psrShow() examples to		 dashes, for aesthetics and compatibility with pretroff.01a,13feb93,jdi  written, based on dbgArchLib.c for mc68k, sparc, and i960.*//*DESCRIPTIONThis module provides architecture-specific support functions for dbgLib.It also includes user-callable functions for accessing the contents ofregisters in a task's TCB (task control block).  These routines include:.TStab(|);l0 l0 l.\&`MC680x0':         | a0() - a7()  | - address registers (`a0' - `a7')         | d0() - d7()  | - data registers (`d0' - `d7')         | sr()         | - status register (`sr')\&`MIPS':  | dbgBpTypeBind() | - bind a breakpoint handler to a breakpoint type\&`x86/SimNT':         | edi() - eax() | - named register values         | eflags()      | - status register value\&`SH':             | r0() - r15() | - general registers (`r0' - `r15')         | sr()         | - status register (`sr')         | gbr()        | - global base register (`gbr')         | vbr()        | - vector base register (`vbr')         | mach()       | - multiply and accumulate register high (`mach')         | macl()       | - multiply and accumulate register low (`macl')         | pr()         | - procedure register (`pr')\&`ARM':         | r0() - r14() | - general-purpose registers (`r0' - `r14')         | cpsr()       | - current processor status reg (`cpsr')         | psrShow()    | - `psr' value, symbolically\&`SimSolaris':         | g0() - g7()  | - global registers (`g0' - `g7')         | o0() - o7()  | - out registers (`o0' - `o7', note lower-case "o")         | l0() - l7()  | - local registers (`l0' - `l7', note lower-case "l")         | i0() - i7()  | - in registers (`i0' - `i7')         | npc()        | - next program counter (`npc')         | psr()        | - processor status register (`psr')         | wim()        | - window invalid mask (`wim')         | y()          | - `y' register .TENOTE:  The routine pc(), for accessing the program counter, is foundin usrLib.SEE ALSO: dbgLib,.pG "Target Shell"INTERNALNote that the program counter (pc) is handled by a non-architecture-specificroutine in usrLib.This module is created by cat'ing together the following files AFTER thefirst entry below - sr(), g0().	mc68k/dbgArchLib.cXX	sparc/dbgArchLib.cXX	i960/dbgArchLib.c	mips/dbgArchLib.c	i86/dbgArchLib.c	sh/dbgArchLib.c	arm/dbgArchLib.c	simsolaris/dbgArchLib.c	simnt/dbgArchLib.c*//********************************************************************************* g0 - return the contents of register `g0', also `g1' - `g7' (SPARC) and `g1' - `g14' (i960)** This command extracts the contents of global register `g0' from the TCB of a* specified task.  If <taskId> is omitted or 0, the current default task is* assumed.** Routines are provided for all global registers:* .TS* tab(|);* l l l.* \&`SPARC':      | g0() - g7()  | (`g0' - `g7')* \&`i960':       | g0() - g14() | (`g0' - `g14')* \&`SimSolaris': | g0() - g7()  | (`g0' - `g7')* .TE** RETURNS: The contents of register `g0' (or the requested register).** SEE ALSO:* .pG "Target Shell"** NOMANUAL*/int g0    (    int taskId		/* task ID, 0 means default task */    )        { ... }/* cat arch libraries after here *//* dbgArchLib.c - MC680x0-dependent debugger library */  /* Copyright 1984-1995 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------01h,10feb95,jdi  doc cleanup for 5.2.01g,13feb93,jdi  documentation cleanup for 5.1; added discrete entry for d0().01f,22sep92,kdl  added single-register display routines, from 5.0 usrLib.01e,19sep92,kdl  made dbgRegsAdjust() clear padding bytes before SR in reg set.01d,23aug92,jcf  changed filename.01c,06jul92,yao  removed dbgCacheClear().  made user uncallable globals		 started with '_'.01b,03jul92,jwt  first pass at converting cache calls to 5.1 cache library.01a,18jun92,yao  written based on mc68k/dbgLib.c ver08g.*//*DESCRIPTIONThis module provides the Motorola 680x0 specific support functions for dbgLib.NOMANUAL*/#include "vxWorks.h"#include "private/dbgLibP.h"#include "taskLib.h"#include "taskArchLib.h"#include "intLib.h"#include "regs.h"#include "iv.h"#include "cacheLib.h"#include "ioLib.h"#include "dsmLib.h"#include "vxLib.h"#include "usrLib.h"/* externals *//* interrupt driver routines from dbgALib.s */IMPORT dbgBpStub ();		/* breakpoint interrupt driver */IMPORT dbgTraceStub ();		/* trace interrupt driver */IMPORT int dsmNbytes ();IMPORT int dsmInst ();/* globals */extern char * _archHelp_msg = "";LOCAL USHORT interruptSR;	/* old SR value before interrupt break *//********************************************************************************* _dbgArchInit - architecture dependent initialization routine** This routine initialize global function pointers that are architecture * specific.** RETURNS: N/A** NOMANUAL*/void _dbgArchInit (void)    {    _dbgDsmInstRtn = (FUNCPTR) dsmInst;    }/********************************************************************************* _dbgVecInit - insert new breakpoint and trace vectors** RETURNS: N/A** NOMANUAL*/void _dbgVecInit (void)        {    /* insert the new breakpoint and trace vectors */    intVecSet ((FUNCPTR *) TRAPNUM_TO_IVEC (DBG_TRAP_NUM), dbgBpStub);    intVecSet ((FUNCPTR *) IV_TRACE, dbgTraceStub);    }/********************************************************************************* _dbgInstSizeGet - set up breakpoint instruction** RETURNS: size of the instruction at specified location.** NOMANUAL*/int _dbgInstSizeGet    (    INSTR * pBrkInst		/* pointer to hold breakpoint instruction */    )    {    return (dsmNbytes (pBrkInst) / sizeof (INSTR));    }/********************************************************************************* _dbgRetAdrsGet - get return address for current routine** RETURNS: return address for current routine.** NOMANUAL*/INSTR * _dbgRetAdrsGet    (    REG_SET * pRegSet		/* pointer to register set */    )    {    /* if next instruction is a LINK or RTS, return address is on top of stack;     * otherwise it follows saved frame pointer */    if (INST_CMP(pRegSet->pc,LINK,LINK_MASK) || 	INST_CMP(pRegSet->pc,RTS,RTS_MASK))        return (*(INSTR **)pRegSet->spReg);    else	return (*((INSTR **)pRegSet->fpReg + 1));    }/********************************************************************************* _dbgSStepClear - clear single step mode** RETURNS: N/A** NOMANUAL*/void _dbgSStepClear (void)    {    }/********************************************************************************* _dbgSStepSet - set single step mode** RETURNS: N/A** NOMANUAL*/void _dbgSStepSet     (    BREAK_ESF * pInfo		/* pointer to info saved on stack */    )    {    pInfo->sr |= TRACE_BIT | 0x700; /* set trace bit and lock interrupts */    }/******************************************************************************** _dbgTaskSStepSet - set single step mode of task** Set the `pcw' and `tcw' of the given task for trace (instruction) break* mode, so that when the task is switched in, it will execute the* next instruction and break.** NOTE* Interrupts are locked out for this task, until single stepping* for the task is cleared.** RETURNS: OK or ERROR if invalid <tid>.** NOMANUAL*/void _dbgTaskSStepSet    (    int tid		/* task's id */    )    {    REG_SET regSet;    taskRegsGet (tid, &regSet);    taskSRSet (tid, regSet.sr | TRACE_BIT);    }/******************************************************************************** _dbgTaskBPModeSet - set breakpoint mode of task** NOMANUAL*/void _dbgTaskBPModeSet     (    int tid		/* task's id */    )    {    }/******************************************************************************** _dbgTaskBPModeClear - clear breakpoint mode of task** NOMANUAL*/void _dbgTaskBPModeClear     (    int tid    )    {    }/********************************************************************************* _dbgFuncCallCheck - check next instruction** This routine checks to see if the next instruction is a JSR or BSR.* If it is, it returns TRUE, otherwise, returns FALSE.** RETURNS: TRUE if next instruction is JSR or BSR, or FALSE otherwise.** NOMANUAL*/BOOL _dbgFuncCallCheck    (    INSTR * addr		/* pointer to instruction */    )    {    return (INST_CMP (addr, JSR, JSR_MASK) || INST_CMP (addr, BSR, BSR_MASK));    }/********************************************************************************* _dbgRegsAdjust - set register set** RETURNS: N/A** NOMANUAL*/void _dbgRegsAdjust    (    FAST int   tid,		/* id of task that hit breakpoint */    TRACE_ESF * pInfo,		/* pointer to esf info saved on stack */    int *       regs,		/* pointer to buf containing saved regs */    BOOL stepBreakFlag		/* TRUE if this was a trace exception */				/* FALSE if this was a SO or CRET breakpoint */    )    {    REG_SET regSet;    int ix;    for (ix = 0; ix < 8; ++ix)	regSet.dataReg [ix] = regs[ix];    for (ix =0; ix < 7; ++ix)	regSet.addrReg [ix] = regs[ix+8];    if (stepBreakFlag)	regSet.spReg = (ULONG) ((char *)pInfo + sizeof (TRACE_ESF));    else	regSet.spReg = (ULONG) ((char *)pInfo + sizeof (BREAK_ESF));    regSet.pc    = pInfo->pc;    regSet.pad   = 0;    regSet.sr    = pInfo->sr;    taskRegsSet (tid, &regSet);    }/********************************************************************************* _dbgIntrInfoSave - restore register set** RETURNS: N/A** NOMANUAL*/void _dbgIntrInfoSave    (    BREAK_ESF * pInfo		/* pointer to info saved on stack */    )    {    interruptSR = pInfo->sr;	/* save SR */    }/******************************************************************************** _dbgIntrInfoRestore - restore the info saved by dbgIntrInfoSave** NOMANUAL*/void _dbgIntrInfoRestore    (    TRACE_ESF *	pBrkInfo	/* pointer to execption frame */    )    {    pBrkInfo->sr = interruptSR;    }/******************************************************************************** _dbgInstPtrAlign - align pointer to appropriate boundary** REUTRNS: align given instruction pointer to appropriate boundary** NOMANUAL*/INSTR * _dbgInstPtrAlign     (    INSTR * addr		/* instuction pointer */    )    {#if (CPU==MC68000 || CPU==MC68010 || CPU==CPU32)    addr = (INSTR *) ((int)addr & ~(0x01));	/* force address even */#endif	/* (CPU==MC68000 || CPU==MC68010 || CPU==CPU32) */    return (addr);    }/********************************************************************************* _dbgInfoPCGet - get pc** RETURNS: value of pc saved on stack** NOMANUAL*/INSTR * _dbgInfoPCGet    (    BREAK_ESF * pInfo		/* pointer to info saved on stack */    )    {    return (pInfo->pc);    }/********************************************************************************* _dbgTaskPCSet - set task's pc** RETURNS: N/A** NOMANUAL*/void _dbgTaskPCSet    (    int    tid,		/* task id */    INSTR* pc,		/* task's pc */    INSTR* npc		/* not supoorted on MC680X0 */    )    {    REG_SET regSet;		/* task's register set */    taskRegsGet (tid, &regSet);    regSet.pc = pc;    taskRegsSet (tid, &regSet);    }/********************************************************************************* _dbgTaskPCGet - restore register set** RETURNS: N/A** NOMANUAL*/INSTR * _dbgTaskPCGet    (    int tid		/* task id */    )    {    REG_SET regSet;		/* task's register set */    taskRegsGet (tid, &regSet);    return (regSet.pc);    }/********************************************************************************