/* cacheArchLib.c - 68K cache management library *//* Copyright 1984-1994 Wind River Systems, Inc. */#include "copyright_wrs.h"/*modification history--------------------03j,29nov95,jdi  doc: fixed typos.03i,02aug95,tpr  added cacheArch060DmaMalloc ().03g,26oct94,tmk  added MC68LC040 support03h,02jun94,tpr  added cacheStoreBufEnable() and cacheStoreBufDisable().		 clean up following code review.		 added MC68060 cpu support.03g,23feb93,jdi  doc: changed cacheArchInvalidate() to refer to 68040 only.03f,15feb93,jdi  made everything NOMANUAL except for cacheArchLibInit() and		 cacheArchClearEntry().03e,10feb93,jwt  added missing address alignment for !ENTIRE_CACHE cases.03d,24jan93,jdi  documentation cleanup for 5.1.03c,22dec92,jwt  added cacheArchInvalidate() for '040 invalidate pointer.03b,19oct92,jcf  fixed writethrough mode cacheFlushRtn.03a,01oct92,jcf  reduced interface to attach to new cacheLib.02l,23sep92,jdi  documentation cleanup, some ansification.02k,23aug92,jcf  changed call to valloc to be indirect.  changed filename.02j,02aug92,jwt  corrected and added "fail" return value for cacheIsOn().02i,31jul92,jwt  converted per buffer function pointers to global; new names.02h,19jul92,jcf  got CPU32 to compile.02g,18jul92,smb  Changed errno.h to errnoLib.h.02f,15jul91,jwt  further refinement of 68K cache library for 5.1:                 freeze -> lock; added address and bytes parameters;                  added cacheMc68kModeSet(); deleted burst routines; cleanup.02e,14jul92,jwt  added missing cacheMc68kFree; cleaned up compiler warnings.02d,13jul92,rdc  added cacheMalloc.02c,03jul92,jwt  first cut at 5.1 cache support; changed name from cacheLib.c.02b,26may92,rrr  the tree shuffle02a,07jan92,jcf  added special 68040 data cache disable routine.		 cleaned up so 68000/68010 don't carry unnecessary luggage.		 obsoleted cacheReset().		 cacheEnable()/cacheDisable() take into account cache state.01f,04oct91,rrr  passed through the ansification filter                  -changed functions to ansi style		  -changed includes to have absolute path from h/		  -fixed #else and #endif		  -changed copyright notice01e,25sep91,yao  added support for CPU32.01d,28aug91,shl  added support for MC68040, added cacheClearPage(),		 updated copyright.01c,28sep90,jcf  documentation.01b,02aug90,jcf  lint.01a,15jul90,jcf  written.*//*DESCRIPTIONThis library contains architecture-specific cache library functions forthe Motorola 68K family instruction and data caches.  The various membersof the 68K family of processors support different cache mechanisms; thus,some operations cannot be performed by certain processors because theylack particular functionalities.  In such cases, the routines in thislibrary return ERROR.  Processor-specific constraints are addressed in themanual entries for routines in this library.  If the caches areunavailable or uncontrollable, the routines return ERROR.  There is nodata cache on the 68020; however, data cache operations return OK.INTERNALThe cache enable and disable processes consist of the following actions,executed by cacheArchEnable() and cacheArchDisable().  To enablea disabled cache, first the cache is fully invalidated.  Then the cache mode (write-through, copy-back, etc.) is configured.  Finally, the cache is turnedon.  Enabling an already enabled cache results in no operation.INTERNALTo disable an enabled cache, first the cache is invalidated.  However, a cacheconfigured in copy-back mode must first have been pushed out to memory.  Onceinvalidated, the cache is turned off.  Disabling an already disabled cacheresults in no operation.For general information about caching, see the manual entry for cacheLib.INCLUDE FILES: cacheLib.hSEE ALSO: cacheLib, vmLibINTERNALThe 68040 has a totally different way of handling its larger caches."burst fill", "freezing", and "clearing" are managed in hardware, or inthe ITT/DTT/PTE entry definitions.  They are NOT direct/simple entries inthe CAAR (which does not exist), or int the CACR (which is now a simpleenable/disable).In addition, the 040 caches are not the simple mechanism used by the020/030: caches may be "non serialized off", "serialized off","write-through", or "copy-back".  And these types may be set individuallybased on decoding an address range through one of four transparanttranslation registers, or through the MMU page table entries (a three-leveltable structure).The 68060 caches are slightly different from the 68040 caches. The inhibitedserialized and non serialized mode was removed and replaced by precise and imprecise mode. But except the names these modes seem to be identical. A four-deep store buffer is added to increase writethrough or imprecise modeperformance. For these modes the store buffer can be enabled or not.A branch cache is also available, linked to the instruction cache to smooththe instruction stream flow thus achieving integer performance level.The frozen cache capability is provided for instruction and data cache.*//* LINTLIBRARY */#include "vxWorks.h"#include "errnoLib.h"#include "cacheLib.h"#include "stdlib.h"#include "private/memPartLibP.h"#include "private/vmLibP.h"#include "private/funcBindP.h"/* forward declarations */LOCAL STATUS	cacheProbe (CACHE_TYPE cache);LOCAL void	cacheSet (CACHE_TYPE cache, int value, int mask);LOCAL BOOL	cacheIsOn (CACHE_TYPE cache);#if	(CPU==MC68060)LOCAL VOID	cacheBranchInv (void);LOCAL void *	cacheArch060DmaMalloc (size_t bytes);#endif	/* (CPU==MC68060) *//********************************************************************************* cacheArchLibInit - initialize the 68K cache library* * This routine initializes the cache library for Motorola MC680x0* processors.  It initializes the function pointers and configures the* caches to the specified cache modes.  Modes should be set before caching* is enabled.  If two complementary flags are set (enable/disable), no* action is taken for any of the input flags.** The caching modes vary for members of the 68K processor family:** .TS* tab(|);* l l l.* 68020: | CACHE_WRITETHROUGH     | (instruction cache only)** 68030: | CACHE_WRITETHROUGH     | *        | CACHE_BURST_ENABLE     |*        | CACHE_BURST_DISABLE    |*        | CACHE_WRITEALLOCATE    | (data cache only)*        | CACHE_NO_WRITEALLOCATE | (data cache only)** 68040: | CACHE_WRITETHROUGH     |*        | CACHE_COPYBACK         | (data cache only)*        | CACHE_INH_SERIAL       | (data cache only)*        | CACHE_INH_NONSERIAL    | (data cache only)*        | CACHE_BURST_ENABLE     | (data cache only)*        | CACHE_NO_WRITEALLOCATE | (data cache only)** 68060: | CACHE_WRITETHROUGH     |*        | CACHE_COPYBACK         | (data cache only)*        | CACHE_INH_PRECISE      | (data cache only)*        | CACHE_INH_IMPRECISE    | (data cache only)*        | CACHE_BURST_ENABLE     | (data cache only)* .TE* * The write-through, copy-back, serial, non-serial, precise and non precise* modes change the state of the data transparent translation register (DTTR0)* CM bits. Only DTTR0 is modified, since it typically maps DRAM space. ** RETURNS: OK.*/STATUS cacheArchLibInit    (    CACHE_MODE	instMode,	/* instruction cache mode */    CACHE_MODE	dataMode	/* data cache mode */    )    {#if ((CPU == MC68020) || (CPU == MC68030) || (CPU == MC68040) || \     (CPU==MC68060) || (CPU == MC68LC040))    cacheLib.enableRtn		= cacheArchEnable;	/* cacheEnable() */    cacheLib.disableRtn		= cacheArchDisable;	/* cacheDisable() */    cacheLib.lockRtn		= cacheArchLock;	/* cacheLock() */    cacheLib.unlockRtn		= cacheArchUnlock;	/* cacheUnlock() */    cacheLib.clearRtn		= cacheArchClear;	/* cacheClear() */    cacheLib.dmaMallocRtn	= (FUNCPTR)cacheArchDmaMalloc;#if	(CPU == MC68060)    if (dataMode & CACHE_SNOOP_ENABLE)	cacheLib.dmaMallocRtn	= (FUNCPTR) cacheArch060DmaMalloc;#endif    cacheLib.dmaFreeRtn		= (FUNCPTR) cacheArchDmaFree;    cacheLib.dmaVirtToPhysRtn	= NULL;    cacheLib.dmaPhysToVirtRtn	= NULL;    cacheLib.textUpdateRtn	= cacheArchTextUpdate;#if ((CPU == MC68020) || (CPU == MC68030))    cacheLib.flushRtn		= NULL;			/* writethrough */    cacheLib.invalidateRtn	= cacheArchClear;	/* cacheFlush() */    cacheLib.pipeFlushRtn	= NULL;#elif ((CPU == MC68040) || (CPU == MC68060) || (CPU == MC68LC040))    cacheLib.flushRtn		= cacheArchClear;	/* cacheFlush() */    cacheLib.invalidateRtn	= cacheArchInvalidate;	/* cacheInvalidate() */    cacheLib.pipeFlushRtn	= (FUNCPTR) cache040WriteBufferFlush;#endif#endif	/* ((CPU==MC68020) || (CPU==MC68030) || (CPU==MC68040) || \	 *  (CPU==MC68060) || (CPU == MC68LC040)) */#if ((CPU == MC68020) || (CPU == MC68030))    /* check for parameter errors */    if (((instMode & CACHE_COPYBACK)) || ((dataMode & CACHE_COPYBACK)) ||	((instMode & (CACHE_SNOOP_ENABLE | CACHE_SNOOP_DISABLE)) != 0) ||	((dataMode & (CACHE_SNOOP_ENABLE | CACHE_SNOOP_DISABLE)) != 0) ||	((instMode & (CACHE_WRITEALLOCATE | CACHE_NO_WRITEALLOCATE)) != 0) ||	((dataMode & CACHE_WRITEALLOCATE)&&(dataMode &CACHE_NO_WRITEALLOCATE))||	((instMode & CACHE_BURST_ENABLE) && (instMode & CACHE_BURST_DISABLE)) ||	((dataMode & CACHE_BURST_ENABLE) && (dataMode & CACHE_BURST_DISABLE)))	return (ERROR);    /* set instruction cache mode attributes */    if (instMode & CACHE_BURST_ENABLE)	cacheSet (INSTRUCTION_CACHE, C_BURST, C_BURST);    if (instMode & CACHE_BURST_DISABLE)	cacheSet (INSTRUCTION_CACHE, 0, C_BURST);    /* set data cache mode attributes */    if (dataMode & CACHE_WRITEALLOCATE)	cacheSet (DATA_CACHE, C_ALLOCATE, C_ALLOCATE);    if (dataMode & CACHE_NO_WRITEALLOCATE) 	cacheSet (DATA_CACHE, 0, C_ALLOCATE);    if (dataMode & CACHE_BURST_ENABLE)	cacheSet (DATA_CACHE, C_BURST, C_BURST);    if (dataMode & CACHE_BURST_DISABLE)	cacheSet (DATA_CACHE, 0, C_BURST);    cacheSet (INSTRUCTION_CACHE, 0, C_ENABLE);	/* turn off instruction cache */    cacheSet (DATA_CACHE, 0, C_ENABLE);		/* turn off data cache */    cacheSet (INSTRUCTION_CACHE, C_CLR, C_CLR);	/* invalidate I-cache entries */    cacheSet (DATA_CACHE, C_CLR, C_CLR);	/* invalidate D-cache entries */#elif ((CPU == MC68040) || (CPU == MC68060) || (CPU == MC68LC040))    /* check for parameter errors */#if 	(CPU == MC68040 || CPU == MC68LC040)    if (((instMode & ~CACHE_WRITETHROUGH) != 0) ||        ((dataMode & CACHE_COPYBACK) && (dataMode & CACHE_WRITETHROUGH)) ||	((dataMode & CACHE_INH_SERIAL) && (dataMode & CACHE_INH_NONSERIAL)) ||	((dataMode & CACHE_SNOOP_ENABLE) && (dataMode & CACHE_SNOOP_DISABLE)) ||	((dataMode & CACHE_WRITEALLOCATE)) ||	((dataMode & CACHE_BURST_DISABLE)))#elif	(CPU == MC68060)    if (((instMode & ~(CACHE_WRITETHROUGH)) !=0) ||	((dataMode & CACHE_COPYBACK) && (dataMode & CACHE_WRITETHROUGH)) ||	((dataMode & CACHE_INH_PRECISE) && (dataMode & CACHE_INH_IMPRECISE)) ||	((dataMode & CACHE_SNOOP_ENABLE) && (dataMode & CACHE_SNOOP_DISABLE)) ||	((dataMode & CACHE_WRITEALLOCATE)) ||	((dataMode & CACHE_NO_WRITEALLOCATE)) ||	((dataMode & CACHE_BURST_DISABLE)))#endif 	return (ERROR);    if (dataMode & CACHE_WRITETHROUGH) 	{	cacheDTTR0ModeSet (C_TTR_WRITETHROUGH);	cacheLib.flushRtn = cacheArchClear;	/* mmu may turn on copy back */	}    else if (dataMode & CACHE_COPYBACK)	{	cacheDTTR0ModeSet (C_TTR_COPYBACK);	cacheLib.flushRtn = cacheArchClear;	}    else#if	(CPU == MC68040 || CPU == MC68LC040)	if (dataMode & CACHE_INH_SERIAL)	{	cacheDTTR0ModeSet (C_TTR_SERIALIZED);	cacheLib.flushRtn = NULL;	}    else if (dataMode & CACHE_INH_NONSERIAL)	{	cacheDTTR0ModeSet (C_TTR_NOT_SERIAL);	cacheLib.flushRtn = (FUNCPTR) cache040WriteBufferFlush;	}#elif	(CPU == MC68060)	if (dataMode & CACHE_INH_PRECISE)	{	cacheDTTR0ModeSet (C_TTR_PRECISE);	cacheLib.flushRtn = NULL;	}    else if (dataMode & CACHE_INH_IMPRECISE)	{	cacheDTTR0ModeSet (C_TTR_NOT_PRECISE);	cacheLib.flushRtn = (FUNCPTR) cache040WriteBufferFlush;	}#endif    cacheSet (INSTRUCTION_CACHE, 0, C_ENABLE);	/* turn off instruction cache */    cacheSet (DATA_CACHE, 0, C_ENABLE);		/* turn off data cache */    cacheCINV (INSTRUCTION_CACHE,CACHE_ALL,0x0);/* invalidate I-cache entries */    cacheCINV (DATA_CACHE, CACHE_ALL, 0x0);	/* invalidate D-cache entries */#endif	/* (CPU == MC68040 || CPU == MC68060 || CPU == MC68LC040) */    cacheDataMode	= dataMode;		/* save dataMode for enable */    cacheDataEnabled	= FALSE;		/* d-cache is currently off */    cacheMmuAvailable	= FALSE;		/* no mmu yet */    return (OK);    }/* No further cache support required MC68000, MC68010, or CPU32 */#if ((CPU==MC68020) || (CPU==MC68030) || (CPU==MC68040) || \     (CPU==MC68060) || (CPU==MC68LC040))/********************************************************************************* cacheArchEnable - enable a 68K cache** This routine enables the specified 68K instruction or data cache.** RETURNS: OK, or ERROR if the cache type is invalid or the cache control* is not supported.** NOMANUAL*/STATUS cacheArchEnable    (    CACHE_TYPE	cache		/* cache to enable */    )    {    if (cacheProbe (cache) != OK)