*		to point to MMU_TRANS_TBL pointer.** NOTE: For MMU library internal use only** RETURNS: index of free array element, or -1 for ERROR.*/LOCAL UINT8 mmu440PidAlloc (MMU_TRANS_TBL *transTbl)    {    int i;    for (i = 1; i < MMU_ADDR_MAP_ARRAY_SIZE; i++)        if (mmuAddrMapArray [i] == MMU_ADDR_MAP_ARRAY_INV)	    {	    mmuAddrMapArray [i] = transTbl;	    return i;	    }    return 0;    }/********************************************************************************* mmu440PidFree - Free (mark as invalid) the pid entry** NOTE: For MMU library internal use only**/LOCAL void mmu440PidFree (UINT8 pid)    {    mmuAddrMapArray [pid] = MMU_ADDR_MAP_ARRAY_INV;    }/********************************************************************************* mmu440TlbDynamicInvalidate - invalidate all dynamic tlb entries** Requires a subsequent context-synchronizing event in order to take effect.** NOTE: For MMU library internal use only.*/LOCAL void mmu440TlbDynamicInvalidate (void)    {    UINT32 index;    UINT32 word0;    for (index = mmuPpcTlbMin; index < mmuPpcTlbMax; index++)	{	/* read current entry -- also sets MMUCR[STID] as a side effect */	word0 = mmuPpcTlbReadEntryWord0 (index);	/* clear valid bit */	word0 &= ~(MMU_STATE_VALID << MMU_STATE_VALID_SHIFT);	/* write back entry -- uses MMUCR[STID] as a side effect */	_WRS_ASM("sync");	mmuPpcTlbWriteEntryWord0 (index, word0);	}	    }/********************************************************************************* mmu440MmucrStidSet - set the STID & STS fields of MMUCR** NOTE: For MMU library internal use only.**/LOCAL void mmu440MmucrStidSet    (    UINT32	stid			/* new stid value */    )    {    MMUCR_REG mmucr;    /* set TID, TS */    mmucr.word = mmuPpcMmucrGet();    mmucr.field.stid = stid;    mmucr.field.sts = 1;    mmuPpcMmucrSet(mmucr.word);    }/********************************************************************************* mmu440Tlbie - Invalidate tlb entry for the specified effective addr** NOTE: For MMU library internal use only.**/LOCAL void mmu440Tlbie (    MMU_TRANS_TBL *	pTransTbl,	/* translation table */    void * effAddr			/* EA to invalidate in tlb */    )    {    UINT32 index;    UINT32 word0;    mmu440MmucrStidSet(pTransTbl->pid);    if ((index = mmuPpcTlbSearch (effAddr)) != -1)	{	/* read current entry -- also sets MMUCR[STID] as a side effect */	word0 = mmuPpcTlbReadEntryWord0 (index);	/* clear valid bit */	word0 &= ~(MMU_STATE_VALID << MMU_STATE_VALID_SHIFT);	if (index < mmuPpcTlbMin)	    {	    /* assertion fails! must not invalidate static entries */#if FALSE	/* useful for debugging */	    strcpy(sysExcMsg, "mmu440Tlbie: static TLB entry invalidated\n");	    sysToMonitor(BOOT_WARM_NO_AUTOBOOT);#endif /* FALSE */	    return; /* ERROR! */	    }	/* write back entry -- uses MMUCR[STID] as a side effect */	_WRS_ASM("sync");	mmuPpcTlbWriteEntryWord0 (index, word0);	}	    }/********************************************************************************* mmu440TlbStaticEntrySet - write a static TLB entry** This function writes one MMU TLB Entry based on the given TLB Entry* Description.** CAVEAT: If previously-enabled caching is being disabled, the caller must* pre-flush or pre-invalidate the appropriate cache lines prior to calling* this function.** NOTE: For MMU library internal use only.**/LOCAL void mmu440TlbStaticEntrySet    (    int		     index,	/* index of TLB Entry to set */    TLB_ENTRY_DESC * pTlbDesc,	/* description of TLB Entry to set */    BOOL	     cacheAllow	/* if TRUE allow caching to be turned on */    )    {    LEVEL_2_DESC	lvl2Desc;	/* TLB entry */    /*     * fill in all fields of a LEVEL_2_DESC with data from the     * TLB_ENTRY_DESC. Use that to write the TLB Entry words.     */    lvl2Desc.field.epn = pTlbDesc->effAddr >> MMU_RPN_SHIFT;    lvl2Desc.field.rsvd1 = 0;    lvl2Desc.field.v = 1;		/* valid */    lvl2Desc.field.ts = ((pTlbDesc->attr & _MMU_TLB_TS_1) ? 1 : 0);    lvl2Desc.field.size =	((pTlbDesc->attr & _MMU_TLB_SZ_MASK) >> _MMU_TLB_SZ_SHIFT);    lvl2Desc.field.rsvd2 = 0;    lvl2Desc.field.rpn = pTlbDesc->realAddr >> MMU_RPN_SHIFT;    lvl2Desc.field.rsvd3 = 0;	    lvl2Desc.field.erpn = pTlbDesc->realAddrExt;    lvl2Desc.field.rsvd4 = 0;	    lvl2Desc.field.u0 = 0;		/* user attribute 0 unused */    lvl2Desc.field.u1 = 0;		/* user attribute 1 unused */    lvl2Desc.field.u2 = 0;		/* user attribute 2 unused */    lvl2Desc.field.u3 = 0;		/* user attribute 3 unused */    if (cacheAllow == TRUE)	{	/* cache as desired */	lvl2Desc.field.w = (pTlbDesc->attr & _MMU_TLB_ATTR_W ? 1 : 0);	lvl2Desc.field.i = (pTlbDesc->attr & _MMU_TLB_ATTR_I ? 1 : 0);	}    else	{	/* cache inhibited -- warning, caller must preflush if necessary */	lvl2Desc.field.w = 0;	lvl2Desc.field.i = 1;	}    lvl2Desc.field.m = 0;		/* memory coherent: no effect */    lvl2Desc.field.g = (pTlbDesc->attr & _MMU_TLB_ATTR_G ? 1 : 0);    lvl2Desc.field.e = 0;		/* big endian */    lvl2Desc.field.rsvd5 = 0;	    lvl2Desc.field.ux = 0;		/* user execute off */    lvl2Desc.field.uw = 0;		/* user write off */    lvl2Desc.field.ur = 0;		/* user read off */    lvl2Desc.field.sx = (pTlbDesc->attr & _MMU_TLB_PERM_X ? 1 : 0);    lvl2Desc.field.sw = (pTlbDesc->attr & _MMU_TLB_PERM_W ? 1 : 0);    lvl2Desc.field.sr = 1;		/* supervisor read on */    /*     * static TLB entries are always written with TID 0 so they will     * match for all settings of the PID register.     */    mmu440MmucrStidSet(0);    /* write current entry -- uses MMUCR[STID] as a side effect */    _WRS_ASM("sync");    mmuPpcTlbWriteEntryWord0 (index, lvl2Desc.words.word0);    mmuPpcTlbWriteEntryWord1 (index, lvl2Desc.words.word1);    mmuPpcTlbWriteEntryWord2 (index, lvl2Desc.words.word2);    }#if FALSE /* unused *//********************************************************************************* mmu440TlbStaticEntryGet - read a static TLB entry** This function reads a MMU TLB Entry and composes a TLB Entry* Description.** NOTE: For MMU library internal use only.**/LOCAL void mmu440TlbStaticEntryGet    (    int		     index,	/* index of TLB Entry to get */    TLB_ENTRY_DESC * pTlbDesc	/* pointer to TLB Entry Description to write */    )    {    LEVEL_2_DESC	lvl2Desc;	/* TLB entry */    /* read entry */    lvl2Desc.words.word0 = mmuPpcTlbReadEntryWord0 (index);    lvl2Desc.words.word1 = mmuPpcTlbReadEntryWord1 (index);    lvl2Desc.words.word2 = mmuPpcTlbReadEntryWord2 (index);    /* translate to a TLB_ENTRY_DESC */    pTlbDesc->effAddr = lvl2Desc.field.epn << MMU_RPN_SHIFT;    pTlbDesc->realAddr = lvl2Desc.field.rpn << MMU_RPN_SHIFT;    pTlbDesc->realAddrExt = lvl2Desc.field.erpn;    pTlbDesc->attr = 0;    pTlbDesc->attr |= (lvl2Desc.field.ts ? _MMU_TLB_TS_1 : 0);    pTlbDesc->attr |= lvl2Desc.field.size << _MMU_TLB_SZ_SHIFT;    pTlbDesc->attr |= (lvl2Desc.field.w ? _MMU_TLB_ATTR_W : 0);    pTlbDesc->attr |= (lvl2Desc.field.i ? _MMU_TLB_ATTR_I : 0);    pTlbDesc->attr |= (lvl2Desc.field.g ? _MMU_TLB_ATTR_G : 0);    pTlbDesc->attr |= (lvl2Desc.field.sx ? _MMU_TLB_PERM_X : 0);    pTlbDesc->attr |= (lvl2Desc.field.sw ? _MMU_TLB_PERM_W : 0);    }#endif /* FALSE - unused *//********************************************************************************* mmu440TlbStaticInit - initialize all static TLB entries** This function initializes MMU TLB Entries from the supplied array of* TLB Entry Descriptions.** CAVEAT: If previously-enabled caching is being disabled, the caller must* pre-flush or pre-invalidate the appropriate cache lines prior to calling* this function.** NOTE: For MMU library internal use only.**/LOCAL void mmu440TlbStaticInit    (    int		     numDescs,	/* number of TLB Entry Descriptors */    TLB_ENTRY_DESC * pTlbDesc,	/* pointer to array of TLB Entries */    BOOL	     cacheAllow	/* if TRUE, caching will be enabled */    )    {    UINT32		index;		/* current index being init'ed */    for (index = 0; index < numDescs; index++, pTlbDesc++)	mmu440TlbStaticEntrySet(index, pTlbDesc, cacheAllow);    }/********************************************************************************* mmu440Show - show the level 1 and 2 descriptor for and effective address** NOTE: For MMU library debug only*/void mmu440Show    (    MMU_TRANS_TBL *	pTransTbl,		/* translation table */    void *		effectiveAddr		/* effective address */    )    {    LEVEL_1_DESC *	pLvl1Desc;	/* level 1 descriptor address */    LEVEL_2_DESC *	pLvl2Desc;	/* level 2 descriptor address */    if (pTransTbl == NULL)	pTransTbl = mmuGlobalTransTbl;    /* get the level 1 descriptor address */    pLvl1Desc = mmu440Lvl1DescAddrGet (pTransTbl, effectiveAddr);    printf ("Level 1:\n");    printf ("l2ba      = 0x%x\n", pLvl1Desc->field.l2ba);    printf ("v         = %d\n", pLvl1Desc->field.v);    if (mmu440Lvl2DescAddrGet (pTransTbl, effectiveAddr, &pLvl2Desc) != OK)	return ;    printf ("\n\n");    printf ("Level 2:\n");    printf ("epn       = 0x%x\n", pLvl2Desc->field.epn);    printf ("v         = %d\n", pLvl2Desc->field.v);    printf ("ts        = %d\n", pLvl2Desc->field.ts);    printf ("size      = 0x%x\n", pLvl2Desc->field.size);    printf ("\n");    printf ("rpn       = 0x%x\n", pLvl2Desc->field.rpn);    printf ("erpn      = 0x%x\n", pLvl2Desc->field.erpn);    printf ("\n");    printf ("u0,1,2,3  = %d,%d,%d,%d\n", pLvl2Desc->field.u0,	pLvl2Desc->field.u1, pLvl2Desc->field.u2, pLvl2Desc->field.u3);    printf ("w,i,m,g,e = %d,%d,%d,%d,%d\n", pLvl2Desc->field.w,	pLvl2Desc->field.i, pLvl2Desc->field.m, pLvl2Desc->field.g,	pLvl2Desc->field.e);    printf ("ux,uw,ur  = %d,%d,%d\n", pLvl2Desc->field.ux,	pLvl2Desc->field.uw, pLvl2Desc->field.ur);    printf ("sx,sw,sr  = %d,%d,%d\n", pLvl2Desc->field.sx,	pLvl2Desc->field.sw, pLvl2Desc->field.sr);    }/******************************************************************************** mmu440TlbShow - Show 440 TLB Entry contents** RETURNS: nothing*/void mmu440TlbShow (void)    {    int	ix;    UINT32 word0, word1, word2;    for (ix=0; ix<64; ix++)	{	word0 = mmuPpcTlbReadEntryWord0 (ix);	word1 = mmuPpcTlbReadEntryWord1 (ix);	word2 = mmuPpcTlbReadEntryWord2 (ix);	printf ("TLB entry %02d : %8x %8x %8x\n", ix, word0, word1, word2);	}    }#ifdef DEBUG_MISS_HANDLER/******************************************************************************** mmu440MetricsShow - Show Miss Handler metrics for debugging** OPTIONS:*	0 or 3 for I-MMU and D-MMU (long)*	1      for I-MMU only (long)*	2      for D-MMU only (long)*	4 or 7 for all metrics (short)*	5      for I-MMU only (short)*	6      for D-MMU only (short)** RETURNS: nothing*/void mmu440MetricsShow    (    UINT32 option    )    {    int		i;		/* index into miss array */    int		firsttime;    UINT32	effAdrs;	/* effective address from miss array */    if (option == 0)	option = 3;    if (option == 4)	option = 7;    if (option & 1)	{	printf ("I-MMU: %d misses, %d errors.",	    mmuPpcITlbMisses, mmuPpcITlbErrors);	if ((option & 4) == 0)	    {	    if (mmuPpcITlbMisses > 0)		printf(" recent misses:");	    i = (int)mmuPpcITlbMisses - 256;	    i = max(0, i);	    for (firsttime=1; i < mmuPpcITlbMisses; i++)		{		if (i % 8 == 0 || firsttime)		    {		    printf("\n %3d ", i);		    firsttime = 0;		    }		effAdrs = mmuPpcITlbMissArray[i % 256] & 0xfffffc00;		printf(" %8x", effAdrs);		}	    }	printf("\n");	}    if (option & 2)	{	printf ("D-MMU: %d misses, %d errors.",	    mmuPpcDTlbMisses, mmuPpcDTlbErrors);	if ((option & 4) == 0)	    {	    if (mmuPpcDTlbMisses > 0)		printf(" recent misses:");	    i = (int)mmuPpcDTlbMisses - 256;	    i = max(0, i);	    for (firsttime=1; i < mmuPpcDTlbMisses; i++)		{		if (i % 8 == 0 || firsttime)		    {		    printf("\n %3d ", i);		    firsttime=0;		    }		effAdrs = mmuPpcDTlbMissArray[i % 256] & 0xfffffc00;		printf(" %8x", effAdrs);		}	    }	printf("\n");	}    }#endif /* DEBUG_MISS_HANDLER */