Version 8.0 Build 215 05/29/2008 SJ Full Version
11
989
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
UART_RX
# storage
db|TEST.(1).cnf
db|TEST.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
UART_RX.vhd
745a13f82aa95143bd2bd24270a2bdf
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sync_clock
50000000
PARAMETER_SIGNED_DEC
USR
baud_rate
9600
PARAMETER_SIGNED_DEC
USR
 constraint(rxd_data)
7 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
TEST
# storage
db|TEST.(0).cnf
db|TEST.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
TEST.vhd
56cda6cbe2e5763631adbab9f77c4b4f
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# hierarchies {
|
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
UART_RX
# storage
db|TEST.(2).cnf
db|TEST.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
UART_RX.vhd
745a13f82aa95143bd2bd24270a2bdf
4
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
sync_clock
50000000
PARAMETER_SIGNED_DEC
USR
baud_rate
115200
PARAMETER_SIGNED_DEC
USR
 constraint(rxd_data)
7 downto 0
PARAMETER_STRING
USR
}
# hierarchies {
UART_RX:RXD_BLOCK
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# complete