?? test.vhd.bak
字號:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TEST IS
PORT(
CLOCK_50 : IN STD_LOGIC;
UART_RXD : IN STD_LOGIC;
SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
UART_TXD : OUT STD_LOGIC;
LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6);
HEX1 : OUT STD_LOGIC_VECTOR(0 TO 6);
HEX2 : OUT STD_LOGIC_VECTOR(0 TO 6);
HEX3 : OUT STD_LOGIC_VECTOR(0 TO 6)
);
END TEST;
ARCHITECTURE STRUCT OF TEST IS
-- COMPONENT ----------------------------
COMPONENT UART_TX
GENERIC(
SYNC_CLOCK : INTEGER := 50000000;
BAUD_RATE : INTEGER := 9600
);
PORT(
CLOCK : IN STD_LOGIC;
TXD_START : IN STD_LOGIC;
TXD_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
TXD : OUT STD_LOGIC;
TXD_BUSY : OUT STD_LOGIC
);
END COMPONENT;
-- SIGNAL -----------------------------
SIGNAL TXD : STD_LOGIC;
SIGNAL TXD_START : STD_LOGIC;
SIGNAL TXD_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TXD_BUSY : STD_LOGIC;
BEGIN
TXD_BLOCK: UART_TX
GENERIC MAP(
50000000, 14400
)
PORT MAP(
CLOCK => CLOCK_50,
TXD_START => TXD_START,
TXD_DATA => TXD_DATA,
TXD => TXD,
TXD_BUSY => TXD_BUSY
);
UART_TXD <= TXD;
TXD_DATA <= SW(7 DOWNTO 0);
TXD_START <= SW(9);
LEDR(9) <= SW(9);
LEDR(7 DOWNTO 0) <= SW(7 DOWNTO 0);
LEDR(8) <= TXD_BUSY;
END STRUCT;
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