|TEST
CLOCK_50 => UART_TX:TXD_BLOCK.CLOCK
UART_RXD => ~NO_FANOUT~
SW[0] => UART_TX:TXD_BLOCK.TXD_DATA[0]
SW[0] => LEDR[0].DATAIN
SW[1] => UART_TX:TXD_BLOCK.TXD_DATA[1]
SW[1] => LEDR[1].DATAIN
SW[2] => UART_TX:TXD_BLOCK.TXD_DATA[2]
SW[2] => LEDR[2].DATAIN
SW[3] => UART_TX:TXD_BLOCK.TXD_DATA[3]
SW[3] => LEDR[3].DATAIN
SW[4] => UART_TX:TXD_BLOCK.TXD_DATA[4]
SW[4] => LEDR[4].DATAIN
SW[5] => UART_TX:TXD_BLOCK.TXD_DATA[5]
SW[5] => LEDR[5].DATAIN
SW[6] => UART_TX:TXD_BLOCK.TXD_DATA[6]
SW[6] => LEDR[6].DATAIN
SW[7] => UART_TX:TXD_BLOCK.TXD_DATA[7]
SW[7] => LEDR[7].DATAIN
SW[8] => ~NO_FANOUT~
SW[9] => UART_TX:TXD_BLOCK.TXD_START
SW[9] => LEDR[9].DATAIN
KEY[0] => ~NO_FANOUT~
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
UART_TXD <= UART_TX:TXD_BLOCK.TXD
LEDR[0] <= SW[0].DB_MAX_OUTPUT_PORT_TYPE
LEDR[1] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE
LEDR[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE
LEDR[3] <= SW[3].DB_MAX_OUTPUT_PORT_TYPE
LEDR[4] <= SW[4].DB_MAX_OUTPUT_PORT_TYPE
LEDR[5] <= SW[5].DB_MAX_OUTPUT_PORT_TYPE
LEDR[6] <= SW[6].DB_MAX_OUTPUT_PORT_TYPE
LEDR[7] <= SW[7].DB_MAX_OUTPUT_PORT_TYPE
LEDR[8] <= UART_TX:TXD_BLOCK.TXD_BUSY
LEDR[9] <= SW[9].DB_MAX_OUTPUT_PORT_TYPE
LEDG[0] <= <GND>
LEDG[1] <= <GND>
LEDG[2] <= <GND>
LEDG[3] <= <GND>
LEDG[4] <= <GND>
LEDG[5] <= <GND>
LEDG[6] <= <GND>
LEDG[7] <= <GND>
HEX0[6] <= <GND>
HEX0[5] <= <GND>
HEX0[4] <= <GND>
HEX0[3] <= <GND>
HEX0[2] <= <GND>
HEX0[1] <= <GND>
HEX0[0] <= <GND>
HEX1[6] <= <GND>
HEX1[5] <= <GND>
HEX1[4] <= <GND>
HEX1[3] <= <GND>
HEX1[2] <= <GND>
HEX1[1] <= <GND>
HEX1[0] <= <GND>
HEX2[6] <= <GND>
HEX2[5] <= <GND>
HEX2[4] <= <GND>
HEX2[3] <= <GND>
HEX2[2] <= <GND>
HEX2[1] <= <GND>
HEX2[0] <= <GND>
HEX3[6] <= <GND>
HEX3[5] <= <GND>
HEX3[4] <= <GND>
HEX3[3] <= <GND>
HEX3[2] <= <GND>
HEX3[1] <= <GND>
HEX3[0] <= <GND>


|TEST|UART_TX:TXD_BLOCK
CLOCK => BAUD_DIVIDER[18].CLK
CLOCK => BAUD_DIVIDER[17].CLK
CLOCK => BAUD_DIVIDER[16].CLK
CLOCK => BAUD_DIVIDER[15].CLK
CLOCK => BAUD_DIVIDER[14].CLK
CLOCK => BAUD_DIVIDER[13].CLK
CLOCK => BAUD_DIVIDER[12].CLK
CLOCK => BAUD_DIVIDER[11].CLK
CLOCK => BAUD_DIVIDER[10].CLK
CLOCK => BAUD_DIVIDER[9].CLK
CLOCK => BAUD_DIVIDER[8].CLK
CLOCK => BAUD_DIVIDER[7].CLK
CLOCK => BAUD_DIVIDER[6].CLK
CLOCK => BAUD_DIVIDER[5].CLK
CLOCK => BAUD_DIVIDER[4].CLK
CLOCK => BAUD_DIVIDER[3].CLK
CLOCK => BAUD_DIVIDER[2].CLK
CLOCK => BAUD_DIVIDER[1].CLK
CLOCK => BAUD_DIVIDER[0].CLK
CLOCK => BAUD_TICK.CLK
CLOCK => SENT_ENABLE.CLK
CLOCK => SENT_DATA[7].CLK
CLOCK => SENT_DATA[6].CLK
CLOCK => SENT_DATA[5].CLK
CLOCK => SENT_DATA[4].CLK
CLOCK => SENT_DATA[3].CLK
CLOCK => SENT_DATA[2].CLK
CLOCK => SENT_DATA[1].CLK
CLOCK => SENT_DATA[0].CLK
CLOCK => SENT_ACTIVE.CLK
TXD_START => SENT_ACTIVE~1.OUTPUTSELECT
TXD_START => START_CONDITION~0.IN1
TXD_DATA[0] => SENT_DATA~7.DATAB
TXD_DATA[1] => SENT_DATA~6.DATAB
TXD_DATA[2] => SENT_DATA~5.DATAB
TXD_DATA[3] => SENT_DATA~4.DATAB
TXD_DATA[4] => SENT_DATA~3.DATAB
TXD_DATA[5] => SENT_DATA~2.DATAB
TXD_DATA[6] => SENT_DATA~1.DATAB
TXD_DATA[7] => SENT_DATA~0.DATAB
TXD <= TXD~reg0.DB_MAX_OUTPUT_PORT_TYPE
TXD_BUSY <= SENT_ENABLE.DB_MAX_OUTPUT_PORT_TYPE