;****************************************************************************
; File Name	: TMS320x240 SPI Master Mode Example Code
;
; TMS320x240 SPI example code #1:  4 Pin SPI option
;                                  - MASTER MODE
;                                  - Interrupts are polled
;                                  - # bytes of data transmitted - 8h
;                                  - # bytes of data received    - 8h
;
*****************************************************************************

; SET statements for '24x devices are device dependent.  The SET locations
; used in this example are typically true for devices with only one SPI
; module.  Consult the device data sheet to determine the exact memory map
; locations of the modules you will be accessing (control registers, RAM,
; ROM).
;                     
     	.include "f240regs.h"    ; contains a list of SET statements 
                                   ; for all registers on TMS320F240.

DP_PF1    .set 224            ; 1st Data Page of peripheral registers (7000h/80h)

; The following SET statements for the SPI are contained in f240regs.h
; and are shown explicitly for clarity.

;Serial Peripheral Interface (SPI) Registers 
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SPICCR       .set   07040h    ; SPI Configuration Control Register
SPICTL       .set   07041h    ; SPI Operation Control Register
SPISTS       .set   07042h    ; SPI Status Register
SPIBRR       .set   07044h    ; SPI Baud Rate Register
SPIEMU       .set   07046h    ; SPI Emulation Buffer Register
SPIBUF       .set   07047h    ; SPI Serial Input Buffer Register
SPIDAT       .set   07049h    ; SPI Serial Data Register
SPIPC1       .set   0704Dh    ; SPI Port Control Register #1
SPIPC2       .set   0704Eh    ; SPI Port Control Register #2
SPIPRI       .set   0704Fh    ; SPI Priority Register

;-----------------------------------------------------------
; Constant definitions
;-----------------------------------------------------------

LENGTH    .set 08h            ; length of the data stream to be
                              ; transmitted/received by SEND_ALL    

;-----------------------------------------------------------
; Variable definitions
;-----------------------------------------------------------

;-----------------------------------------------------------
; The transmit and receive buffer locations are defined below.
; The actual .bss location will need to be defined in the 
; linker control file.
;
     .bss DATAOUT,LENGTH ; Location of LENGTH byte character stream
                         ; transmitted by the SEND_ALL routine.
     .bss DATAIN,LENGTH  ; Location of LENGTH byte character stream
                         ; received by the SEND_ALL routine.
;-----------------------------------------------------------
SPI_DONE  .set 070h      ; Defined B2 RAM location '70h' as SPI transmit
                         ; status location.  1=complete, 0=not complete

;-----------------------------------------------------------
; Macro definitions
;-----------------------------------------------------------
KICK_DOG	.macro			;Watchdog reset macro
		LDP	#00E0h
		SPLK	#05555h, WDKEY
		SPLK	#0AAAAh, WDKEY
		LDP	#0h
		.endm
;===========================================================
; Initialized data for SEND_ALL subroutine
;===========================================================
     .data
TXDATA    .word     01h,02h,04h,08h,10h,20h,40h,80h

;===========================================================
; Reset & interrupt vectors
;===========================================================
	.sect	"vectors"
RSVECT    B    START	; PM 0    Reset Vector	    1
INT1      B    PHANTOM	; PM 2    Int level 1	    4
INT2      B    PHANTOM	; PM 4	Int level 2	    5
INT3      B    PHANTOM	; PM 6	Int level 3	    6
INT4      B    PHANTOM	; PM 8	Int level 4	    7
INT5      B    PHANTOM	; PM A	Int level 5	    8
INT6      B    PHANTOM	; PM C	Int level 6	    9
RESERVED  B    PHANTOM	; PM E	(Analysis Int)    10
SW_INT8   B    PHANTOM	; PM 10   User S/W int	    -
SW_INT9   B    PHANTOM	; PM 12   User S/W int	    -
SW_INT10  B    PHANTOM	; PM 14   User S/W int	    -
SW_INT11  B    PHANTOM	; PM 16   User S/W int	    -
SW_INT12  B    PHANTOM	; PM 18   User S/W int	    -
SW_INT13  B    PHANTOM	; PM 1A   User S/W int	    -
SW_INT14  B    PHANTOM	; PM 1C   User S/W int	    -
SW_INT15  B    PHANTOM	; PM 1E   User S/W int	    -
SW_INT16  B    PHANTOM	; PM 20   User S/W int	    -
TRAP      B    PHANTOM	; PM 22   Trap vector	    -
NMI       B    PHANTOM	; PM 24   Non maskable Int   3
EMU_TRAP  B    PHANTOM	; PM 26   Emulator Trap	    2
SW_INT20  B    PHANTOM	; PM 28   User S/W int	    -
SW_INT21  B    PHANTOM	; PM 2A   User S/W int	    -
SW_INT22  B    PHANTOM	; PM 2C   User S/W int	    -
SW_INT23  B    PHANTOM	; PM 2E   User S/W int	    -


; Begin the Reset initialization here ...
		.text
START:
	CLRC	SXM		     ; Clear Sign Extension Mode
	CLRC	OVM		     ; Reset Overflow Mode

* Set Data Page pointer to  page 1 of the peripheral frame
	LDP	#DP_PF1		; Page DP_PF1 includes WET through EINT frames

* initialize WDT registers
     SPLK #06Fh, WDCR    ; clear WDFLAG, Disable WDT, set WDT for 1 second overflow (max)
     SPLK #07h, RTICR    ; clear RTI Flag, set RTI for 1 second overflow (max)

* configure PLL for 10MHz osc, 10MHz SYSCLK and 20MHz CPUCLK
     SPLK #00B1h,CKCR1   ; CLKIN(OSC)=10MHz,CPUCLK=20MHz
	SPLK	#00C3h,CKCR0   ; CLKMD=PLL Enable,SYSCLK=CPUCLK/2,
     
* Clear reset flag bits in SYSSR (PORRST, PLLRST, ILLRST, SWRST, WDRST) 
	LACL	SYSSR		; ACCL <= SYSSR
	AND	#00FFh		; Clear upper 8 bits of SYSSR
	SACL	SYSSR		; Load new value into SYSSR

* Initialize IOPC1/CLKOUT pin for use as DSP clock out
	SPLK	#40C8h,SYSCR	; No reset, CLKOUT=CPUCLK, VCCA on

* initialize B2 RAM to zero's.
     LAR  AR1,#B2_SADDR  ; AR1 <= B2 start address 
     MAR  *,AR1          ; use B2 start address for next indirect
     ZAC                 ; ACC <= 0
     RPT  #1fh           ; set repeat counter for 1fh+1=20h or 32 loops
     SACL *+             ; write zeros to B2 RAM

* initialize DATAOUT with data to be transmitted.
     LAR  AR1,#DATAOUT   ; AR1 <= DATAOUT start address
     RPT  #07h           ; set repeat counter for 7h+1=8h or 8 loops
     BLPD #TXDATA,*+     ; loads 60h - 68h with 01, 02, 04, ... , 40, 80h
     
     CALL INIT_SPI

; Main routine goes here.  Whenever the data stream previously loaded
; into the DATAOUT location is desired to be transmitted,
; the SEND_ALL subroutine is called.
MAIN                     ; Main loop of code begins here ...

;    ....                ; insert actual code here

     CALL SEND_ALL       ; Call the SEND_ALL subroutine and when it is 
                         ; finished, continue with the MAIN loop.

;    ....                ; insert actual code here

STOP     B    STOP       ; The MAIN program loop has completed one
                         ; pass, for testing purposes, the program 
					; stops here.

*******************************************************************************
*                Subroutines                                                  *
*******************************************************************************
;===========================================================================
; Routine Name: INIT_SPI 	      Routine Type: SR
;
; Description: This SR initializes the SPI for data stream transfer
;              to a slave SPI.  The '240 SPI is configured for
;              8-bit transfers as a master.
;
;===========================================================================
INIT_SPI:
* initialize SPI in master mode
	SPLK	#0087h,SPICCR	; Reset SPI by writing 1 to SWRST
	SPLK	#000Ch,SPICTL	; Disable ints & TALK, normal clock, master mode
	SPLK	#0000h,SPIPRI	; Set SPI interrupt to high priority.
                         ; For emulation purposes, allow the SPI
                         ; to continue after an XDS suspension.
                         ; HAS NO EFFECT ON THE ACTUAL DEVICE.
	SPLK	#000Eh,SPIBRR	; Set baud rate to 'fastest'

; NOTE: The baud rate should be as fast as possible for communications
;       between two or more SPI's.  Issues in the baud rate selection to
;       remember are the master vs. slave maximum speed differences, and
;       to a lessor degree, the clock speed of each device.  For DSP 
;       controllers and PRISM devices this determined by SYSCLK .
;
;       A value of '0Eh' in the SPIBRR will insure the fastest available
;       baud rate for the master and slave device (assuming two DSP controller
;       devices with the same SYSCLK are doing the communication).  This 
;	is true for the case when the master SPI uses a polling routine to
;	determine when to tranmsit the next byte.  

	SPLK	#0000h,SPISTS	; Clear the SPI interrupt status bits
	SPLK	#000Eh,SPICTL	; Enable TALK, CLK ph 1, master mode
	SPLK	#0052h,SPIPC1	; Enable the SPICLK pin function.
                         ; SPISTE will always be general I/O when
                         ; SPI is in master mode, regardless of 
                         ; function bit state.  Set SPISTE as output
                         ; high - disable receiver SPI output.
	SPLK	#0022h,SPIPC2	; Set SIMO & SOMI functions to serial I/O
	SPLK	#0007h,SPICCR	; Release SWRST, clock polarity 0, 8 bits

     RET                 ; Return to MAIN routine.

;===========================================================================
; Routine Name: SEND_ALL	      Routine Type: SR
;
; Description: This SR performs the data stream transfer.  Data to be 
;              transmitted is located at DATAOUT.  Received Data is stored
;              at DATAIN.  This routine polls the SPI INT FLAG bit,
;              SPISTS.6, to determine when each byte transfer has 
;              completed.  The number of bytes transfered is controlled
;              by the constant LENGTH, which is determined prior to 
;              assembly.
;
;===========================================================================
SEND_ALL:
     LAR  AR1,#LENGTH-1  ; load length of data stream into AR1
                         ; and use for transmit/receive loop counter.
     LAR  AR2,#DATAOUT   ; load location of transmit data stream into 
                         ; AR2.
     LAR  AR3,#DATAIN    ; load location of receive data stream into 
                         ; AR3.
     MAR  *,AR2          ; use DATAOUT for next indirect address

; Perform a read-modify-write on SPIPC1 to set SPISTE pin active low
; and enable the slave SPI.
     LACL SPIPC1         ; load contents of SPIPC1 into ACC.
     AND  #0BFh          ; clear SPIPC1.6 to make SPISTE pin active
                         ; low.
     SACL SPIPC1         ; store ACC out to SPIPC1.

LOOP
; Begin Xmit by writing byte to SPIDAT.
	LACL	*+,AR3		; ACC <= byte to xmit
                         ; Increment AR2 by one to point to next byte
                         ; in data stream.
                         ; use DATAIN for next indirect address
	SACL	SPIDAT		; Xmit byte

POLL LACL SPISTS         ; Poll the INT Flag Bit to determine when
                         ; to begin next xmit
	AND	#040h		; Clear all bits except SPI INT FLAG bit
     XOR  #040h          ; ACC=0 if bit is set
     BCND POLL,NEQ       ; continue polling if ACC != 0.

     LACL SPIBUF         ; load the received byte into ACC.
     SACL *+,AR1         ; save the received byte to DATAIN
                         ; increment AR3 by one point to next
                         ; DATAIN location.
                         ; use AR1, # bytes left to tranfer, 
                         ; for next indirect address.
     BANZ LOOP,AR2       ; Branch to LOOP if AR1 is not zero,
                         ; decrement AR1 by one,
                         ; use DATAOUT address for next address

; Optional code section:  This code loads a value into B2 RAM to 
;                         inform the MAIN routine that the data
;                         stream transfer is complete.

     LAR  AR4,#SPI_DONE  ; load address of SPI status location
                         ; into AR4
     MAR  *,AR4          ; use SPI status location for next indirect
     SPLK #01h,*         ; write '01h' into status location to indicate
                         ; data stream transfer is complete.

; Perform a read-modify-write on SPIPC1 to set SPISTE pin active high
; and disable the slave SPI.
     LACL SPIPC1         ; load contents of SPIPC1 into ACC.
     OR   #040h          ; set SPIPC1.6 to make SPISTE pin active
                         ; high.
     SACL SPIPC1         ; store ACC out to SPIPC1.

     RET                 ; Return to MAIN routine.

*******************************************************************************
*                ISR's                                                        *
*******************************************************************************
;==============================================================================
; I S R  -  PHANTOM
;
; Description:	ISR used to trap spurious interrupts.
;
;==============================================================================
PHANTOM 	
END	B	END		; 
     .end