; traffic.v                        ; yes             ; User Verilog HDL File  ; C:/Users/123/Desktop/traffic/traffic.v ;
+----------------------------------+-----------------+------------------------+----------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 58    ;
;     -- Combinational with no register       ; 29    ;
;     -- Register only                        ; 0     ;
;     -- Combinational with a register        ; 29    ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 22    ;
;     -- 3 input functions                    ; 13    ;
;     -- 2 input functions                    ; 22    ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 58    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 11    ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 29    ;
; I/O pins                                    ; 26    ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 29    ;
; Total fan-out                               ; 257   ;
; Average fan-out                             ; 3.06  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |traffic                   ; 58 (58)     ; 29           ; 0           ; 26   ; 0            ; 29 (29)      ; 0 (0)             ; 29 (29)          ; 0 (0)           ; 0 (0)      ; |traffic            ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------+
; State Machine - |traffic|countb                                             ;
+------------+------------+------------+------------+------------+------------+
; Name       ; countb.011 ; countb.010 ; countb.001 ; countb.000 ; countb.100 ;
+------------+------------+------------+------------+------------+------------+
; countb.000 ; 0          ; 0          ; 0          ; 0          ; 0          ;
; countb.001 ; 0          ; 0          ; 1          ; 1          ; 0          ;
; countb.010 ; 0          ; 1          ; 0          ; 1          ; 0          ;
; countb.011 ; 1          ; 0          ; 0          ; 1          ; 0          ;
; countb.100 ; 0          ; 0          ; 0          ; 1          ; 1          ;
+------------+------------+------------+------------+------------+------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------+
; State Machine - |traffic|counta                                ;
+------------+------------+------------+------------+------------+
; Name       ; counta.011 ; counta.010 ; counta.001 ; counta.000 ;
+------------+------------+------------+------------+------------+
; counta.000 ; 0          ; 0          ; 0          ; 0          ;
; counta.001 ; 0          ; 0          ; 1          ; 1          ;
; counta.010 ; 0          ; 1          ; 0          ; 1          ;
; counta.011 ; 1          ; 0          ; 0          ; 1          ;
+------------+------------+------------+------------+------------+


+--------------------------------------------------------------------+
; Registers Removed During Synthesis                                 ;
+----------------------------------------+---------------------------+
; Register name                          ; Reason for Removal        ;
+----------------------------------------+---------------------------+
; countb~57                              ; Lost fanout               ;
; countb~58                              ; Lost fanout               ;
; counta~47                              ; Lost fanout               ;
; counta~48                              ; Lost fanout               ;
; counta~49                              ; Lost fanout               ;
; counta.011                             ; Merged with LAMPA[0]~reg0 ;
; counta.001                             ; Merged with LAMPA[1]~reg0 ;
; counta.010                             ; Merged with LAMPA[2]~reg0 ;
; counta.000                             ; Merged with LAMPA[3]~reg0 ;
; countb.100                             ; Merged with LAMPB[0]~reg0 ;
; countb.010                             ; Merged with LAMPB[1]~reg0 ;
; Total Number of Removed Registers = 11 ;                           ;
+----------------------------------------+---------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 29    ;
; Number of registers using Synchronous Clear  ; 3     ;
; Number of registers using Synchronous Load   ; 10    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 15    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; LAMPA[3]~reg0                          ; 6       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |traffic|LAMPB[0]~reg0     ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |traffic|LAMPA[0]~reg0     ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numa[7]           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numa[5]           ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |traffic|numa[0]           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numb[5]           ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |traffic|numb[4]           ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |traffic|numb[0]           ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |traffic|countb~9          ;
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |traffic|counta~7          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+