//-----------------------------------------------------------------------// Design    : nova// Author(s) : Ke Xu// Email	   : eexuke@yahoo.com// File      : DF_pipeline.v// Generated : Dec 2, 2005// Copyright (C) 2008 Ke Xu                //-------------------------------------------------------------------------------------------------// Description // 5-stage pipeline control for deblocking filter//-------------------------------------------------------------------------------------------------// synopsys translate_off`include "timescale.v"// synopsys translate_on`include "nova_defines.v"module DF_pipeline (clk,gclk_DF,gclk_end_of_MB_DEC,reset_n,disable_DF,end_of_BS_DEC,	end_of_MB_DF,end_of_lastMB_DF,	bs_V0,bs_V1,bs_V2,bs_V3,bs_H0,bs_H1,bs_H2,bs_H3,	QPy,QPc,slice_alpha_c0_offset_div2,slice_beta_offset_div2,	DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout,	buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3,	buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3,		DF_duration,	DF_edge_counter_MR,DF_edge_counter_MW,	one_edge_counter_MR,one_edge_counter_MW,	bs_curr_MR,bs_curr_MW,	p0_MW,p1_MW,p2_MW,p3_MW,q0_MW,q1_MW,q2_MW,q3_MW);	input clk;	input gclk_DF;	input gclk_end_of_MB_DEC;	input reset_n;	input disable_DF;	input end_of_BS_DEC;	input end_of_MB_DF;	input end_of_lastMB_DF;	input [11:0] bs_V0,bs_V1,bs_V2,bs_V3;	input [11:0] bs_H0,bs_H1,bs_H2,bs_H3;	input [5:0] QPy,QPc;	input [3:0]	slice_alpha_c0_offset_div2,slice_beta_offset_div2;	input [31:0] DF_mbAddrA_RF_dout,DF_mbAddrB_RAM_dout,rec_DF_RAM_dout;	input [31:0] buf0_0,buf0_1,buf0_2,buf0_3,buf1_0,buf1_1,buf1_2,buf1_3;	input [31:0] buf2_0,buf2_1,buf2_2,buf2_3,buf3_0,buf3_1,buf3_2,buf3_3;		output DF_duration;	output [5:0] DF_edge_counter_MR,DF_edge_counter_MW;	output [1:0] one_edge_counter_MR,one_edge_counter_MW;	output [2:0] bs_curr_MR;	output [2:0] bs_curr_MW;	output [7:0] p0_MW,p1_MW,p2_MW,p3_MW;	output [7:0] q0_MW,q1_MW,q2_MW,q3_MW;		reg DF_duration;	always @ (posedge clk or negedge reset_n)		if (reset_n == 1'b0)			DF_duration <= 1'b0;		else if (end_of_BS_DEC)			DF_duration <= 1'b1;		else if (end_of_MB_DF || end_of_lastMB_DF)			DF_duration <= 1'b0;		//---------------------------------------------------------------------	//1.MR: Memory Read	//---------------------------------------------------------------------	//DF_edge_counter_MR & one_edge_counter_MR	reg [5:0] DF_edge_counter_MR;	reg [1:0] one_edge_counter_MR;	always @ (posedge gclk_DF or negedge reset_n)		if (reset_n == 1'b0)			DF_edge_counter_MR <= 6'd48;		else if (end_of_BS_DEC == 1'b1)			DF_edge_counter_MR <= 0;		else if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd48)			DF_edge_counter_MR <= DF_edge_counter_MR + 1;			always @ (posedge gclk_DF or negedge reset_n)		if (reset_n == 0)			one_edge_counter_MR <= 2'd3;		else if (end_of_BS_DEC == 1'b1)			one_edge_counter_MR <= 2'd0;		else  			begin				if (one_edge_counter_MR == 2'd3 && DF_edge_counter_MR != 6'd47 && DF_edge_counter_MR[5:4] != 2'b11) //!47,!48					one_edge_counter_MR <= 2'd0;				else if (one_edge_counter_MR != 2'd3)					one_edge_counter_MR <= one_edge_counter_MR + 1;			end		//lumaEdgeFlag_MR,chromaEdgeFlag_MR	wire lumaEdgeFlag_MR,chromaEdgeFlag_MR;	assign lumaEdgeFlag_MR   = !DF_edge_counter_MR[5];	assign chromaEdgeFlag_MR =  DF_edge_counter_MR[5] && (DF_edge_counter_MR != 6'd48);		//bs_curr_MR	reg [2:0] bs_curr_MR;	always @ (disable_DF or lumaEdgeFlag_MR or chromaEdgeFlag_MR or 		DF_edge_counter_MR[4:0] or one_edge_counter_MR[1] or		bs_V0 or bs_V1 or bs_V2 or bs_V3 or bs_H0 or bs_H1 or bs_H2 or bs_H3)		if (!disable_DF && lumaEdgeFlag_MR)			case (DF_edge_counter_MR[4:0])				5'd0 :bs_curr_MR <= bs_V0[2:0];				5'd1 :bs_curr_MR <= bs_V1[2:0];				5'd2 :bs_curr_MR <= bs_V0[5:3];				5'd3 :bs_curr_MR <= bs_V1[5:3];				5'd4 :bs_curr_MR <= bs_H0[2:0];				5'd5 :bs_curr_MR <= bs_H1[2:0];				5'd6 :bs_curr_MR <= bs_V2[2:0];				5'd7 :bs_curr_MR <= bs_V2[5:3];				5'd8 :bs_curr_MR <= bs_H0[5:3];				5'd9 :bs_curr_MR <= bs_H1[5:3];				5'd10:bs_curr_MR <= bs_V3[2:0];				5'd11:bs_curr_MR <= bs_V3[5:3];				5'd12:bs_curr_MR <= bs_H0[8:6];				5'd13:bs_curr_MR <= bs_H0[11:9];				5'd14:bs_curr_MR <= bs_H1[8:6];				5'd15:bs_curr_MR <= bs_H1[11:9];				5'd16:bs_curr_MR <= bs_V0[8:6];				5'd17:bs_curr_MR <= bs_V1[8:6];				5'd18:bs_curr_MR <= bs_V0[11:9];				5'd19:bs_curr_MR <= bs_V1[11:9];				5'd20:bs_curr_MR <= bs_H2[2:0];				5'd21:bs_curr_MR <= bs_H3[2:0];				5'd22:bs_curr_MR <= bs_V2[8:6];				5'd23:bs_curr_MR <= bs_V2[11:9];				5'd24:bs_curr_MR <= bs_H2[5:3];				5'd25:bs_curr_MR <= bs_H3[5:3];				5'd26:bs_curr_MR <= bs_V3[8:6];				5'd27:bs_curr_MR <= bs_V3[11:9];				5'd28:bs_curr_MR <= bs_H2[8:6];				5'd29:bs_curr_MR <= bs_H2[11:9];				5'd30:bs_curr_MR <= bs_H3[8:6];				5'd31:bs_curr_MR <= bs_H3[11:9];			endcase		else if (!disable_DF && chromaEdgeFlag_MR)			case (DF_edge_counter_MR[3:0])				4'd0,4'd8:	//32,40				case (one_edge_counter_MR[1])					1'b0:bs_curr_MR <= bs_V0[2:0];					1'b1:bs_curr_MR <= bs_V0[5:3];				endcase				4'd2,4'd10:	//34,42				case (one_edge_counter_MR[1])					1'b0:bs_curr_MR <= bs_V0[8:6];					1'b1:bs_curr_MR <= bs_V0[11:9];				endcase				4'd1,4'd9:	//33,41				case (one_edge_counter_MR[1])					1'b0:bs_curr_MR <= bs_V2[2:0];					1'b1:bs_curr_MR <= bs_V2[5:3];				endcase				4'd3,4'd11:	//35,43				case (one_edge_counter_MR[1])					1'b0:bs_curr_MR <= bs_V2[8:6];					1'b1:bs_curr_MR <= bs_V2[11:9];				endcase				4'd4,4'd12:	//36,44				case (one_edge_counter_MR[1])					1'b0:bs_curr_MR <= bs_H0[2:0];					1'b1:bs_curr_MR <= bs_H0[5:3];				endcase				4'd5,4'd13:	//37,45				case (one_edge_counter_MR[1])					1'b0:bs_curr_MR <= bs_H0[8:6];					1'b1:bs_curr_MR <= bs_H0[11:9];				endcase				4'd6,4'd14:	//38,46				case (one_edge_counter_MR[1])					1'b0:bs_curr_MR <= bs_H2[2:0];					1'b1:bs_curr_MR <= bs_H2[5:3];				endcase				4'd7,4'd15:	//39,47				case (one_edge_counter_MR[1])					1'b0:bs_curr_MR <= bs_H2[8:6];					1'b1:bs_curr_MR <= bs_H2[11:9];				endcase			endcase		else			bs_curr_MR <= 0;					//	Pipelined parameters	reg [2:0] bs_curr_TD;	reg lumaEdgeFlag_TD,chromaEdgeFlag_TD;	reg [5:0] DF_edge_counter_TD;	reg [1:0] one_edge_counter_TD;	always @ (posedge gclk_DF or negedge reset_n)		if (reset_n == 1'b0)			begin				bs_curr_TD 			<= 0;				lumaEdgeFlag_TD 	<= 0; 					chromaEdgeFlag_TD	<= 0;				DF_edge_counter_TD	<= 6'd48;				one_edge_counter_TD <= 2'd3;			end			else			begin				bs_curr_TD 			<= bs_curr_MR;				lumaEdgeFlag_TD 	<= lumaEdgeFlag_MR; 				chromaEdgeFlag_TD 	<= chromaEdgeFlag_MR;				DF_edge_counter_TD 	<= DF_edge_counter_MR;				one_edge_counter_TD	<= one_edge_counter_MR;			end	//---------------------------------------------------------------------	//2.TD: Threshold Decider	//---------------------------------------------------------------------	wire [6:0] indexA_y_unclipped,indexA_c_unclipped;	wire [6:0] indexB_y_unclipped,indexB_c_unclipped;	assign indexA_y_unclipped = QPy + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0};	assign indexA_c_unclipped = QPc + {{2{slice_alpha_c0_offset_div2[3]}},slice_alpha_c0_offset_div2,1'b0};	assign indexB_y_unclipped = QPy + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0};	assign indexB_c_unclipped = QPc + {{2{slice_beta_offset_div2[3]}},slice_beta_offset_div2,1'b0};		wire [5:0] indexA_y,indexA_c;	wire [5:0] indexB_y,indexB_c;	assign indexA_y = (indexA_y_unclipped[6] == 1)? 0:((indexA_y_unclipped[5:0] > 6'd51)? 6'd51:indexA_y_unclipped[5:0]);	assign indexA_c = (indexA_c_unclipped[6] == 1)? 0:((indexA_c_unclipped[5:0] > 6'd51)? 6'd51:indexA_c_unclipped[5:0]);	assign indexB_y = (indexB_y_unclipped[6] == 1)? 0:((indexB_y_unclipped[5:0] > 6'd51)? 6'd51:indexB_y_unclipped[5:0]);	assign indexB_c = (indexB_c_unclipped[6] == 1)? 0:((indexB_c_unclipped[5:0] > 6'd51)? 6'd51:indexB_c_unclipped[5:0]);		reg [5:0] indexA_y_reg,indexA_c_reg;	reg [5:0] indexB_y_reg,indexB_c_reg;	always @ (posedge gclk_end_of_MB_DEC or negedge reset_n)		if (reset_n == 1'b0)			begin	indexA_y_reg <= 0;	indexA_c_reg <= 0;	indexB_y_reg <= 0;	indexB_c_reg <= 0; end		else if (!disable_DF)			begin				indexA_y_reg <= indexA_y;	indexA_c_reg <= indexA_c;				indexB_y_reg <= indexB_y;	indexB_c_reg <= indexB_c;			end				wire [5:0] indexA,indexB;	assign indexA = (lumaEdgeFlag_TD)? indexA_y_reg:((chromaEdgeFlag_TD)? indexA_c_reg:0);	assign indexB = (lumaEdgeFlag_TD)? indexB_y_reg:((chromaEdgeFlag_TD)? indexB_c_reg:0);		reg [7:0] alpha,beta;	//alpha	always @ (indexA)		if (indexA < 16)			alpha <= 0;		else 			case (indexA)				6'd16,6'd17:alpha <= 8'd4;				6'd18:alpha <= 8'd5;	6'd19:alpha <= 8'd6;	6'd20:alpha <= 8'd7;	6'd21:alpha <= 8'd8;				6'd22:alpha <= 8'd9;	6'd23:alpha <= 8'd10;	6'd24:alpha <= 8'd12;	6'd25:alpha <= 8'd13;				6'd26:alpha <= 8'd15;	6'd27:alpha <= 8'd17;	6'd28:alpha <= 8'd20;	6'd29:alpha <= 8'd22;				6'd30:alpha <= 8'd25;	6'd31:alpha <= 8'd28;	6'd32:alpha <= 8'd32;	6'd33:alpha <= 8'd36;				6'd34:alpha <= 8'd40;	6'd35:alpha <= 8'd45;	6'd36:alpha <= 8'd50;	6'd37:alpha <= 8'd56;				6'd38:alpha <= 8'd63;	6'd39:alpha <= 8'd71;	6'd40:alpha <= 8'd80;	6'd41:alpha <= 8'd90;				6'd42:alpha <= 8'd101;	6'd43:alpha <= 8'd113;	6'd44:alpha <= 8'd127;	6'd45:alpha <= 8'd144;				6'd46:alpha <= 8'd162;	6'd47:alpha <= 8'd182;	6'd48:alpha <= 8'd203;	6'd49:alpha <= 8'd226;				default:alpha <= 8'd255;			endcase	//beta	always @ (indexB)		if (indexB < 16)			beta <= 0;		else if (indexB > 15 && indexB < 26) 			case (indexB)				6'd16,6'd17,6'd18		:beta <= 8'd2;				6'd19,6'd20,6'd21,6'd22	:beta <= 8'd3;				6'd23,6'd24,6'd25		:beta <= 8'd4;				default:beta <= 0;			endcase		else 			beta <= indexB[5:1] - 3'd7; 		wire [7:0] absolute_TD0_a,absolute_TD0_b;	wire [7:0] absolute_TD1_a,absolute_TD1_b;	wire [7:0] absolute_TD2_a,absolute_TD2_b;	wire [7:0] absolute_TD0_out,absolute_TD1_out,absolute_TD2_out;	absolute absolute_TD0 (.a(absolute_TD0_a),.b(absolute_TD0_b),.out(absolute_TD0_out));	absolute absolute_TD1 (.a(absolute_TD1_a),.b(absolute_TD1_b),.out(absolute_TD1_out));	absolute absolute_TD2 (.a(absolute_TD2_a),.b(absolute_TD2_b),.out(absolute_TD2_out));		//p0 ~ p3	wire Is_p_from_mbAddrA;	wire Is_p_from_mbAddrB;	wire Is_p_from_buf0;	wire Is_p_from_buf1;	wire Is_p_from_buf2;	wire Is_p_from_buf3;	assign Is_p_from_mbAddrA =    (DF_edge_counter_TD == 6'd0  || DF_edge_counter_TD == 6'd2  ||	DF_edge_counter_TD == 6'd16 || DF_edge_counter_TD == 6'd18 || DF_edge_counter_TD == 6'd32 ||	DF_edge_counter_TD == 6'd34 || DF_edge_counter_TD == 6'd40 || DF_edge_counter_TD == 6'd42);		assign Is_p_from_mbAddrB =    (DF_edge_counter_TD == 6'd4  || DF_edge_counter_TD == 6'd8  ||