; 78K/0 Series C Compiler V4.00 Assembler Source
;                                                Date: 7 Apr 2009 Time:10:48:16

; Command   : -cF0411 -yd:\program files\nec electronics tools\dev -_msgoff -a 
;             -zpn -w0 -no system.c
; In-file   : system.c
; Asm-file  : system.asm
; Para-file : 

$PROCESSOR(F0411)
$DEBUG
$NODEBUGA
$KANJICODE NONE
$TOL_INF	03FH, 0400H, 00H, 020H, 00H

$DGS	FIL_NAM, .file,		020H,	0FFFEH,	03FH,	067H,	01H,	00H
$DGS	AUX_FIL, system.c
$DGS	MOD_NAM, system,	00H,	0FFFEH,	00H,	077H,	00H,	00H
$DGS	SEC_NAM, @@BITS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CNST,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@R_INIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INIT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATA,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@R_INIS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@INIS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@DATS,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CALT,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CODE,	U,	U,	00H,	078H,	00H,	00H
$DGS	SEC_NAM, @@CALF,	U,	U,	00H,	078H,	00H,	00H
$DGS	GLV_SYM, _Clock_Init,	U,	U,	08001H,	020H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	01AH,	00H
$DGS	BEG_FUN, ??bf_Clock_Init,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 034H,		02H,	014H
$DGS	REG_VAR, _temp_stabset,	06H,	0FFFFH,	010CH,	04H,	00H,	00H
$DGS	REG_VAR, _temp_stabwait,	07H,	0FFFFH,	010CH,	04H,	00H,	00H
$DGS	BEG_BLK, ??bb00_Clock_Init,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_BEG, 0CH,		00H,	00H
$DGS	END_BLK, ??eb00_Clock_Init,	U,	U,	00H,	064H,	01H,	00H
$DGS	AUX_END, 0FH
$DGS	END_FUN, ??ef_Clock_Init,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 01CH
$DGS	GLV_SYM, _sub_clock_init,	U,	U,	08001H,	020H,	01H,	02H
$DGS	AUX_FUN, 00H,		U,	U,	020H,	00H
$DGS	BEG_FUN, ??bf_sub_clock_init,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_BEG, 052H,		00H,	020H
$DGS	END_FUN, ??ef_sub_clock_init,	U,	U,	00H,	065H,	01H,	00H
$DGS	AUX_END, 09H

	PUBLIC	_Clock_Init
	PUBLIC	_sub_clock_init

@@BITS	BSEG

@@CNST	CSEG	UNITP

@@R_INIT	CSEG	UNITP

@@INIT	DSEG	UNITP

@@DATA	DSEG	UNITP

@@R_INIS	CSEG	UNITP

@@INIS	DSEG	SADDRP

@@DATS	DSEG	SADDRP

@@CALT	CSEG	CALLT0

; line    35
; line    36
; line    37
; line    38
; line    39
; line    40
; line    52

@@CODE	CSEG
_Clock_Init:
$DGL	1,14
	push	hl						;[INF] 1, 4
??bf_Clock_Init:
; line    56
$DGL	0,5
	mov	a,PM12						;[INF] 2, 5
	or	a,#06H	; 6 					;[INF] 2, 4
	mov	PM12,a						;[INF] 2, 5
; line    57
$DGL	0,6
	mov	a,OSCCTL					;[INF] 2, 5
	and	a,#07FH	; 127 					;[INF] 2, 4
	mov	OSCCTL,a					;[INF] 2, 5
; line    58
$DGL	0,7
	mov	a,OSCCTL					;[INF] 2, 5
	or	a,#040H	; 64 					;[INF] 2, 4
	mov	OSCCTL,a					;[INF] 2, 5
; line    59
$DGL	0,8
	mov	a,MOC						;[INF] 2, 5
	and	a,#07FH	; 127 					;[INF] 2, 4
	mov	MOC,a						;[INF] 2, 5
; line    62
$DGL	0,11
	mov	l,#01FH	; 31 					;[INF] 2, 4
; line    63
?L0003:
??bb00_Clock_Init:
; line    64
$DGL	0,13
	mov	a,OSTC						;[INF] 2, 5
	mov	h,a						;[INF] 1, 2
; line    65
$DGL	0,14
	mov	a,l						;[INF] 1, 2
	and	h,a						;[INF] 2, 4
??eb00_Clock_Init:
; line    66
$DGL	0,15
	mov	a,h						;[INF] 1, 2
	cmp	a,l						;[INF] 2, 4
	bnz	$?L0003						;[INF] 2, 6
; line    69
$DGL	0,18
	mov	OSTS,#05H	; 5 				;[INF] 3, 7
; line    70
$DGL	0,19
	mov	a,OSCCTL					;[INF] 2, 5
	and	a,#0FEH	; 254 					;[INF] 2, 4
	mov	OSCCTL,a					;[INF] 2, 5
; line    71
$DGL	0,20
	mov	a,MCM						;[INF] 2, 5
	or	a,#05H	; 5 					;[INF] 2, 4
	mov	MCM,a						;[INF] 2, 5
; line    72
$DGL	0,21
	mov	a,PM12						;[INF] 2, 5
	or	a,#018H	; 24 					;[INF] 2, 4
	mov	PM12,a						;[INF] 2, 5
; line    73
$DGL	0,22
	mov	a,OSCCTL					;[INF] 2, 5
	and	a,#0DFH	; 223 					;[INF] 2, 4
	mov	OSCCTL,a					;[INF] 2, 5
; line    75
$DGL	0,24
	mov	a,OSCCTL					;[INF] 2, 5
	or	a,#010H	; 16 					;[INF] 2, 4
	mov	OSCCTL,a					;[INF] 2, 5
; line    77
$DGL	0,26
	mov	a,RCM						;[INF] 2, 5
	and	a,#0FEH	; 254 					;[INF] 2, 4
	mov	RCM,a						;[INF] 2, 5
; line    78
$DGL	0,27
	mov	PCC,#00H	; 0 				;[INF] 3, 7
; line    79
$DGL	0,28
??ef_Clock_Init:
	pop	hl						;[INF] 1, 4
	ret							;[INF] 1, 6
??ee_Clock_Init:
; line    82
_sub_clock_init:
$DGL	1,26
??bf_sub_clock_init:
; line    83
$DGL	0,2
	set1	MOC.7						;[INF] 3, 8
; line    84
$DGL	0,3
	mov	OSCCTL,#010H	; 16 				;[INF] 3, 7
; line    86
$DGL	0,5
	mov	WDTE,#0ACH	; 172 				;[INF] 3, 7
; line    87
$DGL	0,6
	set1	PCC.4						;[INF] 3, 8
; line    88
$DGL	0,7
?L0008:
	bt	PCC.5,$?L0009					;[INF] 4,11
	br	$?L0008						;[INF] 2, 6
?L0009:
; line    89
$DGL	0,8
	set1	RCM.0						;[INF] 3, 8
; line    90
$DGL	0,9
??ef_sub_clock_init:
	ret							;[INF] 1, 6
??ee_sub_clock_init:

@@CALF	CSEG	FIXED
	END


; *** Code Information ***
;
; $FILE E:\06 Water Clear\code\waterflow\system.c
;
; $FUNC Clock_Init(52)
;	void=(void)
;	CODE SIZE= 82 bytes, CLOCK_SIZE= 197 clocks, STACK_SIZE= 2 bytes
;
; $FUNC sub_clock_init(82)
;	void=(void)
;	CODE SIZE= 22 bytes, CLOCK_SIZE= 61 clocks, STACK_SIZE= 0 bytes

; Target chip : uPD78F0411
; Device file : V1.11