?? lpc32x0.s
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EMCAHBTimeOut4_Val EQU 0x00000190
;// </e> End of Dynamic Setup for CS0 Area
;// <e> Configure External Bus Behaviour for Dynamic CS1 Area
EMC_DYNCS1_SETUP EQU 0
;// <h> Dynamic Memory Configuration Register (EMCDynamicConfig1)
;// <i> Defines the configuration information for the dynamic memory CS1
;// <o0.20> P: Write protect enable
;// <o0.7..14> AM: Address Mapping
;// <0=> 16 bit
;// <1=> 32 bit
;// <o0.14> AM 14: External bus data width
;// <0=> 16 bit
;// <1=> 32 bit
;// <o0.12..13> AM 13..12: External bus memory type
;// <0=> High-performance
;// <1=> Low-power SDRAM
;// <o0.7..11> AM 11..7: External bus address mapping (Row, Bank, Column)
;// <0x00=> 16 Mb = 2MB (2Mx8), 2 banks, row length = 11, column length = 9
;// <0x01=> 16 Mb = 2MB (1Mx16), 2 banks, row length = 11, column length = 8
;// <0x04=> 64 Mb = 8MB (8Mx8), 4 banks, row length = 12, column length = 9
;// <0x05=> 64 Mb = 8MB (4Mx16), 4 banks, row length = 12, column length = 8
;// <0x08=> 128 Mb = 16MB (16Mx8), 4 banks, row length = 12, column length = 10
;// <0x09=> 128 Mb = 16MB (8Mx16), 4 banks, row length = 12, column length = 9
;// <0x0C=> 256 Mb = 32MB (32Mx8), 4 banks, row length = 13, column length = 10
;// <0x0D=> 256 Mb = 32MB (16Mx16), 4 banks, row length = 13, column length = 9
;// <0x10=> 512 Mb = 64MB (64Mx8), 4 banks, row length = 13, column length = 11
;// <0x11=> 512 Mb = 64MB (32Mx16), 4 banks, row length = 13, column length = 10
;// <o0.3..4> MD: Memory device
;// <0=> SDR SDRAM
;// <2=> Low-power SDR SDRAM
;// <4=> DDR SDRAM
;// <6=> Low-power DDR SDRAM
;// </h>
EMCDynConfig1_Val EQU 0x00000000
;// <h> Dynamic Memory RAS & CAS Delay register (EMCDynamicRASCAS1)
;// <i> Controls the RAS and CAS latencies for the dynamic memory CS1
;// <o0.7..10 > CAS: CAS latency
;// <1=> 0.5 clock cycle
;// <2=> 1 clock cycles
;// <3=> 1.5 clock cycle
;// <4=> 2 clock cycles
;// <5=> 2.5 clock cycle
;// <6=> 3 clock cycles
;// <7=> 3.5 clock cycle
;// <8=> 4 clock cycles
;// <9=> 4.5 clock cycle
;// <10=> 5 clock cycles
;// <11=> 5.5 clock cycle
;// <12=> 6 clock cycles
;// <13=> 6.5 clock cycle
;// <14=> 7 clock cycles
;// <15=> 7.5 clock cycle
;// <o0.0..3> RAS: RAS latency (active to read/write delay, in clock cycles) <1-15>
;// </h>
EMCDynRasCas1_Val EQU 0x00000303
;// </e> End of Dynamic Setup for CS1 Area
;// </e> End of Dynamic Setup
;// Static Memory Interface Setup ----------------------------------------
;// <e> Static Memory Interface Setup
EMC_STATIC_SETUP EQU 0
;// Configure External Bus Behaviour for Static CS0 Area ---------------
;// <e> Configure External Bus Behaviour for Static CS0 Area
EMC_STACS0_SETUP EQU 1
;// <h> Static Memory Configuration Register (EMCStaticConfig0)
;// <i> Defines the configuration information for the static memory CS0
;// <o0.20> WP: Write protect enable
;// <o0.8> EW: Extended wait enable
;// <o0.7> PB: Byte lane state
;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW
;// <1=> For reads BLSn are LOW, for writes BLSn are LOW
;// <o0.6> PC: Chip select polarity
;// <0=> Active LOW chip select
;// <1=> Active HIGH chip select
;// <o0.3> PM: Page mode enable
;// <o0.0..1> MW: Memory width
;// <0=> 8 bit
;// <1=> 16 bit
;// <2=> 32 bit
;// </h>
EMCStaConfig0_Val EQU 0x00000081
;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen0)
;// <i> Selects the delay from CS0 to write enable
;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitWen0_Val EQU 0x00000000
;// <h> Static Memory Output Enable Delay Register (EMCStaticWaitOen0)
;// <i> Selects the delay from CS0 or address change, whichever is later, to output enable
;// <o.0..3> WAITOEN: Wait output enable <0-15>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitOen0_Val EQU 0x00000000
;// <h> Static Memory Read Delay Register (EMCStaticWaitRd0)
;// <i> Selects the delay from CS0 to a read access
;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitRd0_Val EQU 0x00000007
;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
;// <i> Selects the delay for asynchronous page mode sequential accesses for CS0
;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitPage0_Val EQU 0x00000000
;// <h> Static Memory Write Delay Register (EMCStaticWaitWr0)
;// <i> Selects the delay from CS0 to a write access
;// <o.0..4> WAITWR: Write wait states <2-33> <#-2>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitWr0_Val EQU 0x00000000
;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn0)
;// <i> Selects the number of bus turnaround cycles for CS0
;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitTurn0_Val EQU 0x00000000
;// </e> End of Static Setup for Static CS0 Area
;// Configure External Bus Behaviour for Static CS1 Area ---------------
;// <e> Configure External Bus Behaviour for Static CS1 Area
EMC_STACS1_SETUP EQU 0
;// <h> Static Memory Configuration Register (EMCStaticConfig1)
;// <i> Defines the configuration information for the static memory CS1
;// <o0.20> WP: Write protect enable
;// <o0.8> EW: Extended wait enable
;// <o0.7> PB: Byte lane state
;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW
;// <1=> For reads BLSn are LOW, for writes BLSn are LOW
;// <o0.6> PC: Chip select polarity
;// <0=> Active LOW chip select
;// <1=> Active HIGH chip select
;// <o0.3> PM: Page mode enable
;// <o0.0..1> MW: Memory width
;// <0=> 8 bit
;// <1=> 16 bit
;// <2=> 32 bit
;// </h>
EMCStaConfig1_Val EQU 0x00000002
;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen1)
;// <i> Selects the delay from CS1 to write enable
;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitWen1_Val EQU 0x00000000
;// <h> Static Memory Output Enable Delay Register (EMCStaticWaitOen1)
;// <i> Selects the delay from CS1 or address change, whichever is later, to output enable
;// <o.0..3> WAITOEN: Wait output enable <0-15>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitOen1_Val EQU 0x00000000
;// <h> Static Memory Read Delay Register (EMCStaticWaitRd1)
;// <i> Selects the delay from CS1 to a read access
;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitRd1_Val EQU 0x0000001F
;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage1)
;// <i> Selects the delay for asynchronous page mode sequential accesses for CS1
;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitPage1_Val EQU 0x0000001F
;// <h> Static Memory Write Delay Register (EMCStaticWaitWr1)
;// <i> Selects the delay from CS1 to a write access
;// <o.0..4> WAITWR: Write wait states <2-33> <#-2>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitWr1_Val EQU 0x0000001F
;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn1)
;// <i> Selects the number of bus turnaround cycles for CS1
;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitTurn1_Val EQU 0x0000000F
;// </e> End of Static Setup for Static CS1 Area
;// Configure External Bus Behaviour for Static CS2 Area ---------------
;// <e> Configure External Bus Behaviour for Static CS2 Area
EMC_STACS2_SETUP EQU 0
;// <h> Static Memory Configuration Register (EMCStaticConfig2)
;// <i> Defines the configuration information for the static memory CS2
;// <o0.20> WP: Write protect enable
;// <o0.8> EW: Extended wait enable
;// <o0.7> PB: Byte lane state
;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW
;// <1=> For reads BLSn are LOW, for writes BLSn are LOW
;// <o0.6> PC: Chip select polarity
;// <0=> Active LOW chip select
;// <1=> Active HIGH chip select
;// <o0.3> PM: Page mode enable
;// <o0.0..1> MW: Memory width
;// <0=> 8 bit
;// <1=> 16 bit
;// <2=> 32 bit
;// </h>
EMCStaConfig2_Val EQU 0x00000002
;// <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen2)
;// <i> Selects the delay from CS2 to write enable
;// <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitWen2_Val EQU 0x00000000
;// <h> Static Memory Output Enable Delay Register (EMCStaticWaitOen2)
;// <i> Selects the delay from CS2 or address change, whichever is later, to output enable
;// <o.0..3> WAITOEN: Wait output enable <0-15>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitOen2_Val EQU 0x00000000
;// <h> Static Memory Read Delay Register (EMCStaticWaitRd2)
;// <i> Selects the delay from CS2 to a read access
;// <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitRd2_Val EQU 0x0000001F
;// <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage2)
;// <i> Selects the delay for asynchronous page mode sequential accesses for CS2
;// <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitPage2_Val EQU 0x0000001F
;// <h> Static Memory Write Delay Register (EMCStaticWaitWr2)
;// <i> Selects the delay from CS2 to a write access
;// <o.0..4> WAITWR: Write wait states <2-33> <#-2>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitWr2_Val EQU 0x0000001F
;// <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn2)
;// <i> Selects the number of bus turnaround cycles for CS2
;// <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
;// <i> The delay is in HCLK cycles
;// </h>
EMCStaWaitTurn2_Val EQU 0x0000000F
;// </e> End of Static Setup for Static CS2 Area
;// Configure External Bus Behaviour for Static CS3 Area ---------------
;// <e> Configure External Bus Behaviour for Static CS3 Area
EMC_STACS3_SETUP EQU 0
;// <h> Static Memory Configuration Register (EMCStaticConfig3)
;// <i> Defines the configuration information for the static memory CS3
;// <o0.20> WP: Write protect enable
;// <o0.8> EW: Extended wait enable
;// <o0.7> PB: Byte lane state
;// <0=> For reads BLSn are HIGH, for writes BLSn are LOW
;// <1=> For reads BLSn are LOW, for writes BLSn are LOW
;// <o0.6> PC: Chip select polarity
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